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From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Fabiano Rosas" <farosas@suse.de>,
	"Laurent Vivier" <lvivier@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v1 01/22] hw/misc/aspeed_hace: Remove unused code for better readability
Date: Fri, 21 Mar 2025 17:25:57 +0800	[thread overview]
Message-ID: <20250321092623.2097234-2-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com>

This cleanup follows significant changes in commit 4c1d0af4a28d, making the
model more readable.

- Deleted "iov_cache" and "iov_count" from "AspeedHACEState".
- Removed "reconstruct_iov" function and related logic.
- Simplified "do_hash_operation" by eliminating redundant checks.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/misc/aspeed_hace.h |  2 --
 hw/misc/aspeed_hace.c         | 35 -----------------------------------
 2 files changed, 37 deletions(-)

diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h
index 5d4aa19cfe..b69a038d35 100644
--- a/include/hw/misc/aspeed_hace.h
+++ b/include/hw/misc/aspeed_hace.h
@@ -31,10 +31,8 @@ struct AspeedHACEState {
     MemoryRegion iomem;
     qemu_irq irq;
 
-    struct iovec iov_cache[ASPEED_HACE_MAX_SG];
     uint32_t regs[ASPEED_HACE_NR_REGS];
     uint32_t total_req_len;
-    uint32_t iov_count;
 
     MemoryRegion *dram_mr;
     AddressSpace dram_as;
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 32a5dbded3..8e7e8113a5 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -137,25 +137,6 @@ static bool has_padding(AspeedHACEState *s, struct iovec *iov,
     return false;
 }
 
-static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id,
-                           uint32_t *pad_offset)
-{
-    int i, iov_count;
-    if (*pad_offset != 0) {
-        s->iov_cache[s->iov_count].iov_base = iov[id].iov_base;
-        s->iov_cache[s->iov_count].iov_len = *pad_offset;
-        ++s->iov_count;
-    }
-    for (i = 0; i < s->iov_count; i++) {
-        iov[i].iov_base = s->iov_cache[i].iov_base;
-        iov[i].iov_len = s->iov_cache[i].iov_len;
-    }
-    iov_count = s->iov_count;
-    s->iov_count = 0;
-    s->total_req_len = 0;
-    return iov_count;
-}
-
 static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
                               bool acc_mode)
 {
@@ -237,19 +218,6 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
         iov[0].iov_base = haddr;
         iov[0].iov_len = len;
         i = 1;
-
-        if (s->iov_count) {
-            /*
-             * In aspeed sdk kernel driver, sg_mode is disabled in hash_final().
-             * Thus if we received a request with sg_mode disabled, it is
-             * required to check whether cache is empty. If no, we should
-             * combine cached iov and the current iov.
-             */
-            s->total_req_len += len;
-            if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) {
-                i = reconstruct_iov(s, iov, 0, &pad_offset);
-            }
-        }
     }
 
     if (acc_mode) {
@@ -273,7 +241,6 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
             qcrypto_hash_free(s->hash_ctx);
 
             s->hash_ctx = NULL;
-            s->iov_count = 0;
             s->total_req_len = 0;
         }
     } else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf,
@@ -432,7 +399,6 @@ static void aspeed_hace_reset(DeviceState *dev)
     }
 
     memset(s->regs, 0, sizeof(s->regs));
-    s->iov_count = 0;
     s->total_req_len = 0;
 }
 
@@ -469,7 +435,6 @@ static const VMStateDescription vmstate_aspeed_hace = {
     .fields = (const VMStateField[]) {
         VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS),
         VMSTATE_UINT32(total_req_len, AspeedHACEState),
-        VMSTATE_UINT32(iov_count, AspeedHACEState),
         VMSTATE_END_OF_LIST(),
     }
 };
-- 
2.43.0


  reply	other threads:[~2025-03-21  9:26 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-21  9:25 [PATCH v1 00/22] Fix incorrect hash results on AST2700 Jamin Lin via
2025-03-21  9:25 ` Jamin Lin via [this message]
2025-04-01 13:08   ` [PATCH v1 01/22] hw/misc/aspeed_hace: Remove unused code for better readability Cédric Le Goater
2025-05-05  3:28     ` Jamin Lin
2025-05-06  9:01       ` Cédric Le Goater
2025-03-21  9:25 ` [PATCH v1 02/22] hw/misc/aspeed_hace: Fix buffer overflow in has_padding function Jamin Lin via
2025-03-21  9:47   ` Jamin Lin
2025-03-22 20:52     ` Cédric Le Goater
2025-03-21  9:25 ` [PATCH v1 03/22] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Jamin Lin via
2025-04-01 13:17   ` Cédric Le Goater
2025-05-09  6:57     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 04/22] hw/misc/aspeed_hace: Update hash source address handling to 64-bit for AST2700 Jamin Lin via
2025-04-01 13:52   ` Cédric Le Goater
2025-05-09  6:49     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 05/22] hw/misc/aspeed_hace: Introduce 64-bit digest_addr variable " Jamin Lin via
2025-04-01 13:55   ` Cédric Le Goater
2025-05-09  4:01     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 06/22] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-01 13:57   ` Cédric Le Goater
2025-05-09  6:55     ` Jamin Lin
2025-05-10  6:12       ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 07/22] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Jamin Lin via
2025-04-01 16:19   ` Cédric Le Goater
2025-05-12  8:06     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 08/22] hw/misc/aspeed_hace: Support DMA 64 bits dram address Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  7:41   ` Cédric Le Goater
2025-05-09  7:04     ` Jamin Lin
2025-05-10  6:15       ` Cédric Le Goater
2025-05-12  8:41         ` Jamin Lin
2025-05-15  7:11           ` Jamin Lin
2025-05-15  7:19             ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 09/22] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Jamin Lin via
2025-04-02  9:35   ` Cédric Le Goater
2025-05-06  5:08     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 10/22] hw/misc/aspeed_hace:: Support setting different memory size Jamin Lin via
2025-04-02  7:46   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 11/22] hw/misc/aspeed_hace: Add trace-events for better debugging Jamin Lin via
2025-04-02  7:59   ` Cédric Le Goater
2025-05-12  1:34     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 12/22] hw/misc/aspeed_hace Support to dump plaintext and digest " Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  8:05   ` Cédric Le Goater
2025-05-12  5:22     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 13/22] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  8:54   ` Cédric Le Goater
2025-05-05  6:42     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 14/22] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  9:43   ` Cédric Le Goater
2025-05-05  3:44     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 15/22] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  9:02   ` Cédric Le Goater
2025-05-05  6:36     ` Jamin Lin
2025-05-05  6:51       ` Jamin Lin
2025-05-06  8:59         ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 16/22] test/qtest/hace: Add SHA-384 tests for AST2600 Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  9:02   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 17/22] test/qtest/hace: Add tests for AST1030 Jamin Lin via
2025-04-02  9:44   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 18/22] test/qtest/hace: Update source data and digest data type to 64-bit Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  9:05   ` Cédric Le Goater
2025-05-12  7:14     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 19/22] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  9:06   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 20/22] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  9:12   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 21/22] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Jamin Lin via
2025-04-02  9:12   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 22/22] test/qtest/hace: Add tests for AST2700 Jamin Lin via
2025-03-21  9:26   ` Jamin Lin via
2025-04-02  9:16   ` Cédric Le Goater
2025-03-21  9:39 ` [PATCH v1 00/22] Fix incorrect hash results on AST2700 Cédric Le Goater
2025-04-02  9:47 ` Cédric Le Goater
2025-04-02  9:54   ` Jamin Lin

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