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Tue, 25 Mar 2025 07:43:00 -0700 (PDT) From: Xu Lu To: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, alex@ghiti.fr Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Xu Lu Subject: [PATCH] iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform Date: Tue, 25 Mar 2025 22:42:52 +0800 Message-Id: <20250325144252.27403-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Introduce a new configuration CONFIG_RISCV_IOMMU_32BIT to enable splitting 8-byte access into 4-byte transactions for hardware platform whose I/O bus limits access to 4-byte transfers. Signed-off-by: Xu Lu --- drivers/iommu/riscv/Kconfig | 9 +++++++++ drivers/iommu/riscv/iommu.h | 28 +++++++++++++++++++++++----- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig index c071816f59a6..b7c9ea22d969 100644 --- a/drivers/iommu/riscv/Kconfig +++ b/drivers/iommu/riscv/Kconfig @@ -18,3 +18,12 @@ config RISCV_IOMMU_PCI def_bool y if RISCV_IOMMU && PCI_MSI help Support for the PCIe implementation of RISC-V IOMMU architecture. + +config RISCV_IOMMU_32BIT + bool "Support 4-Byte Accesses on RISC-V IOMMU Registers" + depends on RISCV_IOMMU + default n + help + Support hardware platform whose I/O bus limits access to 4-byte + transfers. When enabled, all accesses to IOMMU registers will be + split into 4-byte accesses. diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..0e3552a8142d 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,6 +14,10 @@ #include #include #include +#ifdef CONFIG_RISCV_IOMMU_32BIT +#include +#include +#endif #include "iommu-bits.h" @@ -69,21 +73,35 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu); #define riscv_iommu_readl(iommu, addr) \ readl_relaxed((iommu)->reg + (addr)) -#define riscv_iommu_readq(iommu, addr) \ - readq_relaxed((iommu)->reg + (addr)) - #define riscv_iommu_writel(iommu, addr, val) \ writel_relaxed((val), (iommu)->reg + (addr)) +#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ + readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ + delay_us, timeout_us) + +#ifndef CONFIG_RISCV_IOMMU_32BIT +#define riscv_iommu_readq(iommu, addr) \ + readq_relaxed((iommu)->reg + (addr)) + #define riscv_iommu_writeq(iommu, addr, val) \ writeq_relaxed((val), (iommu)->reg + (addr)) #define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \ delay_us, timeout_us) +#else /* CONFIG_RISCV_IOMMU_32BIT */ +#define riscv_iommu_readq(iommu, addr) \ + hi_lo_readq_relaxed((iommu)->reg + (addr)) -#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ - readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ +#define riscv_iommu_writeq(iommu, addr, val) \ + ((addr == RISCV_IOMMU_REG_IOHPMCYCLES) ? \ + lo_hi_writeq_relaxed((val), (iommu)->reg + (addr)) : \ + hi_lo_writeq_relaxed((val), (iommu)->reg + (addr))) + +#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ + readx_poll_timeout(hi_lo_readq_relaxed, (iommu)->reg + (addr), val, cond, \ delay_us, timeout_us) +#endif /* CONFIG_RISCV_IOMMU_32BIT */ #endif -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81196C3600C for ; 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Tue, 25 Mar 2025 07:43:00 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.58]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22780f39656sm90623745ad.5.2025.03.25.07.42.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Mar 2025 07:43:00 -0700 (PDT) From: Xu Lu To: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, alex@ghiti.fr Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Xu Lu Subject: [PATCH] iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform Date: Tue, 25 Mar 2025 22:42:52 +0800 Message-Id: <20250325144252.27403-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250325_074306_307323_5267F6E4 X-CRM114-Status: UNSURE ( 8.31 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Introduce a new configuration CONFIG_RISCV_IOMMU_32BIT to enable splitting 8-byte access into 4-byte transactions for hardware platform whose I/O bus limits access to 4-byte transfers. Signed-off-by: Xu Lu --- drivers/iommu/riscv/Kconfig | 9 +++++++++ drivers/iommu/riscv/iommu.h | 28 +++++++++++++++++++++++----- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig index c071816f59a6..b7c9ea22d969 100644 --- a/drivers/iommu/riscv/Kconfig +++ b/drivers/iommu/riscv/Kconfig @@ -18,3 +18,12 @@ config RISCV_IOMMU_PCI def_bool y if RISCV_IOMMU && PCI_MSI help Support for the PCIe implementation of RISC-V IOMMU architecture. + +config RISCV_IOMMU_32BIT + bool "Support 4-Byte Accesses on RISC-V IOMMU Registers" + depends on RISCV_IOMMU + default n + help + Support hardware platform whose I/O bus limits access to 4-byte + transfers. When enabled, all accesses to IOMMU registers will be + split into 4-byte accesses. diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..0e3552a8142d 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,6 +14,10 @@ #include #include #include +#ifdef CONFIG_RISCV_IOMMU_32BIT +#include +#include +#endif #include "iommu-bits.h" @@ -69,21 +73,35 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu); #define riscv_iommu_readl(iommu, addr) \ readl_relaxed((iommu)->reg + (addr)) -#define riscv_iommu_readq(iommu, addr) \ - readq_relaxed((iommu)->reg + (addr)) - #define riscv_iommu_writel(iommu, addr, val) \ writel_relaxed((val), (iommu)->reg + (addr)) +#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ + readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ + delay_us, timeout_us) + +#ifndef CONFIG_RISCV_IOMMU_32BIT +#define riscv_iommu_readq(iommu, addr) \ + readq_relaxed((iommu)->reg + (addr)) + #define riscv_iommu_writeq(iommu, addr, val) \ writeq_relaxed((val), (iommu)->reg + (addr)) #define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \ delay_us, timeout_us) +#else /* CONFIG_RISCV_IOMMU_32BIT */ +#define riscv_iommu_readq(iommu, addr) \ + hi_lo_readq_relaxed((iommu)->reg + (addr)) -#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ - readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ +#define riscv_iommu_writeq(iommu, addr, val) \ + ((addr == RISCV_IOMMU_REG_IOHPMCYCLES) ? \ + lo_hi_writeq_relaxed((val), (iommu)->reg + (addr)) : \ + hi_lo_writeq_relaxed((val), (iommu)->reg + (addr))) + +#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ + readx_poll_timeout(hi_lo_readq_relaxed, (iommu)->reg + (addr), val, cond, \ delay_us, timeout_us) +#endif /* CONFIG_RISCV_IOMMU_32BIT */ #endif -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv