From: Siddharth Menon <simeddon@gmail.com>
To: linux-iio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev,
gregkh@linuxfoundation.org, jic23@kernel.org,
Michael.Hennerich@analog.com, lars@metafoo.de,
marcelo.schmitt1@gmail.com, Siddharth Menon <simeddon@gmail.com>
Subject: [PATCH] iio: frequency: ad9832: Update bit manipulation macros to use FIELD_PREP and GENMASK
Date: Wed, 26 Mar 2025 18:43:03 +0530 [thread overview]
Message-ID: <20250326131338.21309-1-simeddon@gmail.com> (raw)
Update AD9832_PHASE and RES_MASK to use FIELD_PREP and GENMASK for
clean bitmask generation and improved maintainability.
Suggested-by: Marcelo Schmitt <marcelo.schmitt1@gmail.com>
Signed-off-by: Siddharth Menon <simeddon@gmail.com>
---
drivers/staging/iio/frequency/ad9832.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c
index 07baa574aa46..1627b0d5de8a 100644
--- a/drivers/staging/iio/frequency/ad9832.c
+++ b/drivers/staging/iio/frequency/ad9832.c
@@ -62,7 +62,7 @@
#define AD9832_CMD_SLEEPRESCLR 0xC
#define AD9832_FREQ BIT(11)
-#define AD9832_PHASE(x) (((x) & 3) << 9)
+#define AD9832_PHASE(x) FIELD_PREP(GENMASK(10, 9), x)
#define AD9832_SYNC BIT(13)
#define AD9832_SELSRC BIT(12)
#define AD9832_SLEEP BIT(13)
@@ -70,7 +70,7 @@
#define AD9832_CLR BIT(11)
#define AD9832_FREQ_BITS 32
#define AD9832_PHASE_BITS 12
-#define RES_MASK(bits) ((1 << (bits)) - 1)
+#define RES_MASK(bits) GENMASK((bits) - 1, 0)
#define AD9832_CMD_MSK GENMASK(15, 12)
#define AD9832_ADD_MSK GENMASK(11, 8)
#define AD9832_DAT_MSK GENMASK(7, 0)
--
2.49.0
reply other threads:[~2025-03-26 13:13 UTC|newest]
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