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From: Cezary Rojewski <cezary.rojewski@intel.com>
To: broonie@kernel.org
Cc: tiwai@suse.com, perex@perex.cz,
	amadeuszx.slawinski@linux.intel.com, linux-sound@vger.kernel.org,
	hdegoede@redhat.com, Cezary Rojewski <cezary.rojewski@intel.com>
Subject: [PATCH 01/12] ALSA: hda: Allow to fetch hlink by ID
Date: Fri,  4 Apr 2025 11:49:42 +0200	[thread overview]
Message-ID: <20250404094953.3657679-2-cezary.rojewski@intel.com> (raw)
In-Reply-To: <20250404094953.3657679-1-cezary.rojewski@intel.com>

Starting with LNL platform, Intel HDAudio Links carry IDs specifying
non-HDAudio transfer type they help facilitate e.g.: 0xC0 for I2S as
defined by AZX_REG_ML_LEPTR_ID_INTEL_SSP.

The mechanism accounts for LEPTR register as it is Reserved if
LCAP.ALT for given Link equals 0.

Reviewed-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
---
 include/sound/hdaudio_ext.h         |  5 +++++
 sound/hda/ext/hdac_ext_controller.c | 18 ++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h
index 4c7a40e149a5..60ec12e3b72f 100644
--- a/include/sound/hdaudio_ext.h
+++ b/include/sound/hdaudio_ext.h
@@ -22,6 +22,7 @@ void snd_hdac_ext_bus_ppcap_enable(struct hdac_bus *chip, bool enable);
 void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_bus *chip, bool enable);
 
 int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_bus *bus);
+struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_id(struct hdac_bus *bus, u32 id);
 struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_addr(struct hdac_bus *bus, int addr);
 struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_name(struct hdac_bus *bus,
 							 const char *codec_name);
@@ -97,12 +98,16 @@ struct hdac_ext_link {
 	void __iomem *ml_addr; /* link output stream reg pointer */
 	u32 lcaps;   /* link capablities */
 	u16 lsdiid;  /* link sdi identifier */
+	u32 id;
 
 	int ref_count;
 
 	struct list_head list;
 };
 
+#define hdac_ext_link_alt(link)		((link)->lcaps & AZX_ML_HDA_LCAP_ALT)
+#define hdac_ext_link_ofls(link)	((link)->lcaps & AZX_ML_HDA_LCAP_OFLS)
+
 int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *hlink);
 int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *hlink);
 int snd_hdac_ext_bus_link_power_up_all(struct hdac_bus *bus);
diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
index 6199bb60ccf0..2ec1531d1c1b 100644
--- a/sound/hda/ext/hdac_ext_controller.c
+++ b/sound/hda/ext/hdac_ext_controller.c
@@ -9,6 +9,7 @@
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 
+#include <linux/bitfield.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <sound/hda_register.h>
@@ -81,6 +82,7 @@ int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_bus *bus)
 	int idx;
 	u32 link_count;
 	struct hdac_ext_link *hlink;
+	u32 leptr;
 
 	link_count = readl(bus->mlcap + AZX_REG_ML_MLCD) + 1;
 
@@ -97,6 +99,11 @@ int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_bus *bus)
 		hlink->lcaps  = readl(hlink->ml_addr + AZX_REG_ML_LCAP);
 		hlink->lsdiid = readw(hlink->ml_addr + AZX_REG_ML_LSDIID);
 
+		if (hdac_ext_link_alt(hlink)) {
+			leptr = readl(hlink->ml_addr + AZX_REG_ML_LEPTR);
+			hlink->id = FIELD_GET(AZX_REG_ML_LEPTR_ID, leptr);
+		}
+
 		/* since link in On, update the ref */
 		hlink->ref_count = 1;
 
@@ -125,6 +132,17 @@ void snd_hdac_ext_link_free_all(struct hdac_bus *bus)
 }
 EXPORT_SYMBOL_GPL(snd_hdac_ext_link_free_all);
 
+struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_id(struct hdac_bus *bus, u32 id)
+{
+	struct hdac_ext_link *hlink;
+
+	list_for_each_entry(hlink, &bus->hlink_list, list)
+		if (hdac_ext_link_alt(hlink) && hlink->id == id)
+			return hlink;
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_get_hlink_by_id);
+
 /**
  * snd_hdac_ext_bus_get_hlink_by_addr - get hlink at specified address
  * @bus: hlink's parent bus device
-- 
2.25.1


  reply	other threads:[~2025-04-04  9:32 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-04  9:49 [PATCH 00/12] ASoC: Intel: avs: Add support for MTL-FCL platforms Cezary Rojewski
2025-04-04  9:49 ` Cezary Rojewski [this message]
2025-04-04  9:49 ` [PATCH 02/12] ASoC: Intel: avs: Ignore Vendor-space manipulation for ACE Cezary Rojewski
2025-04-04  9:49 ` [PATCH 03/12] ASoC: Intel: avs: Read HW capabilities when possible Cezary Rojewski
2025-04-04  9:49 ` [PATCH 04/12] ASoC: Intel: avs: Relocate DSP status registers Cezary Rojewski
2025-04-04  9:49 ` [PATCH 05/12] ASoC: Intel: avs: MTL-based platforms support Cezary Rojewski
2025-04-04  9:49 ` [PATCH 06/12] ASoC: Intel: avs: LNL-based " Cezary Rojewski
2025-04-04  9:49 ` [PATCH 07/12] ASoC: Intel: avs: PTL-based " Cezary Rojewski
2025-04-04  9:49 ` [PATCH 08/12] ASoC: Intel: avs: PCM operations for LNL-based platforms Cezary Rojewski
2025-04-04  9:49 ` [PATCH 09/12] ASoC: Intel: avs: Dynamically assign ops for non-HDAudio DAIs Cezary Rojewski
2025-04-04  9:49 ` [PATCH 10/12] ASoC: Intel: avs: Conditionally add DMA config when creating Copier Cezary Rojewski
2025-04-04  9:49 ` [PATCH 11/12] ASoC: Intel: avs: Add boards definitions for ACE platforms Cezary Rojewski
2025-04-04  9:49 ` [PATCH 12/12] ALSA: hda: Select avs-driver by default on FCL Cezary Rojewski
2025-04-04 12:52 ` [PATCH 00/12] ASoC: Intel: avs: Add support for MTL-FCL platforms Girdwood, Liam R
2025-04-04 13:09   ` Cezary Rojewski
2025-04-04 13:28     ` Girdwood, Liam R
2025-04-07  8:04       ` Cezary Rojewski
2025-04-07  9:36         ` Girdwood, Liam R
2025-04-07  9:45           ` Cezary Rojewski
2025-04-07 10:15             ` Girdwood, Liam R

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