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[36.231.65.80]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22ac7c992aasm36686985ad.157.2025.04.10.16.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 16:36:27 -0700 (PDT) From: Chao-ying Fu X-Google-Original-From: Chao-ying Fu To: opensbi@lists.infradead.org Cc: Chao-ying Fu Subject: [PATCH v3 7/9] platform: generic: mips: add a dts file Date: Thu, 10 Apr 2025 15:45:33 -0700 Message-ID: <20250410224536.25021-8-cfu@mips.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_163629_998651_D87A6C56 X-CRM114-Status: GOOD ( 12.06 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org We add a dts file for 4 cores 2 threads each on a Boston board. Signed-off-by: Chao-ying Fu --- platform/generic/mips/mips,boston-p8700.dts | 339 ++++++++++++++++++++ 1 file changed, 339 insertions(+) create mode 100644 platform/generic/mips/mips,boston-p8700.dts diff --git a/platform/generic/mips/mips,boston-p8700.dts b/platform/generic/mips/mips,boston-p8700.dts new file mode 100644 index 0000000..a8de86e --- /dev/null +++ b/platform/generic/mips/mips,boston-p8700.dts @@ -0,0 +1,339 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 MIPS + * + */ + +/dts-v1/; + +#define CM_BASE 0x16100000 +#define APLIC_M_BASE (CM_BASE + 0x40000) +#define APLIC_S_BASE (CM_BASE + 0x60000) +#define MSWI_BASE (CM_BASE + 0x50000) +#define MTIMER_BASE (MSWI_BASE + 0x4000) +#define CPC_TIMER (CM_BASE + 0x8050) + +#define IRQ_TYPE_LEVEL_HIGH 4 +#define UART_INT 4 +#define PCIE2_INT 7 + +#define BITFILE_FREQUENCY 25000000 + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "MIPS P8700"; + compatible = "mips,p8700"; + + chosen { + stdout-path = &uart0; + // For Qemu + //bootargs = "root=/dev/sda rw earlycon console=ttyS0,115200n8r"; + // For a Boston board + bootargs = "root=/dev/mmcblk0p5 rw rootwait earlycon console=ttyS0,115200n8r"; + + opensbi-domains { + compatible = "opensbi,domain,config"; + + tmem: tmem { + compatible = "opensbi,domain,memregion"; + base = <0x0 0x80000000>; + order = <31>; + }; + + allmem: allmem { + compatible = "opensbi,domain,memregion"; + base = <0x0 0x0>; + order = <64>; + }; + + tdomain: trusted-domain { + compatible = "opensbi,domain,instance"; + possible-harts = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5 &cpu6 &cpu7>; + regions = <&tmem 0x3f>, <&allmem 0x3f>; + }; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = ; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000000>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000001>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000010>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000011>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000020>; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000021>; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000030>; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdcsu"; + status = "okay"; + reg = <0x00000031>; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + pci2: pci@14000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x14000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&aplic_s0>; + interrupts = ; + + ranges = <0x02000000 0 0x16000000 + 0x16000000 0 0x100000>; + + bus-range = <0x00 0xff>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci2_intc 1>, + <0 0 0 2 &pci2_intc 2>, + <0 0 0 3 &pci2_intc 3>, + <0 0 0 4 &pci2_intc 4>; + + pci2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + pci2_root@0,0 { + compatible = "pci10ee,7021", "pci-bridge"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_bridge@1,0,0 { + compatible = "pci8086,8800", "pci-bridge"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802", "intel,pch-gbe"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 1>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803", "intel,eg20t-gpio"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; + + eg20t_i2c@2,12,2 { + compatible = "pci8086,8817"; + reg = <0x00026200 0 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + rtc@68 { + compatible = "st,m41t81s"; + reg = <0x68>; + }; + }; + }; + }; + }; + + uart0: uart@17ffe000 { + compatible = "ns16550a"; + reg = <0x17ffe000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + + interrupt-parent = <&aplic_s0>; + interrupts = ; + + clock-frequency = ; + + u-boot,dm-pre-reloc; + }; + + lcd: lcd@17fff000 { + compatible = "img,boston-lcd"; + reg = <0x17fff000 0x8>; + }; + + flash@18000000 { + compatible = "cfi-flash"; + reg = <0x18000000 0x8000000>; + bank-width = <2>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aplic_s0: interrupt-controller@16160000 { + #interrupt-cells = <0x00000002>; + compatible = "riscv,aplic"; + interrupt-controller; + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>, <&cpu4_intc 9>, <&cpu5_intc 9>, <&cpu6_intc 9>, <&cpu7_intc 9>; + reg = ; + riscv,num-sources = <0x00000035>; + }; + + aplic_m0: interrupt-controller@16140000 { + #interrupt-cells = <0x00000002>; + riscv,delegate = <&aplic_s0 0x00000001 0x00000035>; + riscv,children = <&aplic_s0>; + compatible = "riscv,aplic"; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, <&cpu2_intc 11>, <&cpu3_intc 11>, <&cpu4_intc 11>, <&cpu5_intc 11>, <&cpu6_intc 11>, <&cpu7_intc 11>; + reg = ; + riscv,num-sources = <0x00000035>; + }; + + mswi0: interrupt-controller@16150000 { + compatible = "riscv,aclint-mswi"; + interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>, <&cpu2_intc 3>, <&cpu3_intc 3>, <&cpu4_intc 3>, <&cpu5_intc 3>, <&cpu6_intc 3>, <&cpu7_intc 3>; + reg = ; + interrupt-controller; + #interrupt-cells = <0>; + }; + + mtimer0: timer@16154000 { + compatible = "riscv,aclint-mtimer"; + reg = , + ; + interrupts-extended = <&cpu0_intc 7>, <&cpu1_intc 7>, <&cpu2_intc 7>, <&cpu3_intc 7>, <&cpu4_intc 7>, <&cpu5_intc 7>, <&cpu6_intc 7>, <&cpu7_intc 7>; + }; + }; +}; -- 2.47.1 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi