From: Mario Limonciello <superm1@kernel.org>
To: "Borislav Petkov" <bp@alien8.de>,
"Jean Delvare" <jdelvare@suse.com>,
"Andi Shyti" <andi.shyti@kernel.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Mario Limonciello <mario.limonciello@amd.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)),
"H . Peter Anvin" <hpa@zytor.com>,
Shyam Sundar S K <Shyam-sundar.S-k@amd.com>,
Hans de Goede <hdegoede@redhat.com>,
linux-doc@vger.kernel.org (open list:DOCUMENTATION),
linux-kernel@vger.kernel.org (open list),
linux-i2c@vger.kernel.org (open list:I2C/SMBUS CONTROLLER
DRIVERS FOR PC),
platform-driver-x86@vger.kernel.org (open list:AMD PMC DRIVER)
Subject: [PATCH v4 3/5] i2c: piix4: Move SB800_PIIX4_FCH_PM_ADDR definition to amd/fch.h
Date: Mon, 14 Apr 2025 19:26:56 -0500 [thread overview]
Message-ID: <20250415002658.1320419-4-superm1@kernel.org> (raw)
In-Reply-To: <20250415002658.1320419-1-superm1@kernel.org>
From: Mario Limonciello <mario.limonciello@amd.com>
SB800_PIIX4_FCH_PM_ADDR is used to indicate the base address for the
FCH PM registers. Multiple drivers may need this base address, so
move it to a common header location and rename accordingly.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
v4:
* Move FCH_PM_DECODEEN to fch.h, but shift it for use in piix4 because
piix4 does 8 bit reads
---
arch/x86/include/asm/amd/fch.h | 12 ++++++++++++
drivers/i2c/busses/i2c-piix4.c | 18 +++++++++---------
2 files changed, 21 insertions(+), 9 deletions(-)
create mode 100644 arch/x86/include/asm/amd/fch.h
diff --git a/arch/x86/include/asm/amd/fch.h b/arch/x86/include/asm/amd/fch.h
new file mode 100644
index 0000000000000..a5fd91ff92df3
--- /dev/null
+++ b/arch/x86/include/asm/amd/fch.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_X86_AMD_FCH_H_
+#define _ASM_X86_AMD_FCH_H_
+
+#define FCH_PM_BASE 0xFED80300
+
+/* register offsets from PM base */
+#define FCH_PM_DECODEEN 0x00
+#define FCH_PM_DECODEEN_SMBUS0SEL GENMASK(20, 19)
+
+#endif
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index dd75916157f05..6350003de32b1 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -21,6 +21,7 @@
an i2c_algorithm to access them.
*/
+#include <asm/amd/fch.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
@@ -80,12 +81,11 @@
#define SB800_PIIX4_PORT_IDX_MASK 0x06
#define SB800_PIIX4_PORT_IDX_SHIFT 1
-/* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
-#define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
-#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
+/* SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
+#define SB800_PIIX4_PORT_IDX_KERNCZ (FCH_PM_DECODEEN + 0x02)
+#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ (FCH_PM_DECODEEN_SMBUS0SEL >> 16)
#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
-#define SB800_PIIX4_FCH_PM_ADDR 0xFED80300
#define SB800_PIIX4_FCH_PM_SIZE 8
#define SB800_ASF_ACPI_PATH "\\_SB.ASFC"
@@ -162,19 +162,19 @@ int piix4_sb800_region_request(struct device *dev, struct sb800_mmio_cfg *mmio_c
if (mmio_cfg->use_mmio) {
void __iomem *addr;
- if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
+ if (!request_mem_region_muxed(FCH_PM_BASE,
SB800_PIIX4_FCH_PM_SIZE,
"sb800_piix4_smb")) {
dev_err(dev,
"SMBus base address memory region 0x%x already in use.\n",
- SB800_PIIX4_FCH_PM_ADDR);
+ FCH_PM_BASE);
return -EBUSY;
}
- addr = ioremap(SB800_PIIX4_FCH_PM_ADDR,
+ addr = ioremap(FCH_PM_BASE,
SB800_PIIX4_FCH_PM_SIZE);
if (!addr) {
- release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
+ release_mem_region(FCH_PM_BASE,
SB800_PIIX4_FCH_PM_SIZE);
dev_err(dev, "SMBus base address mapping failed.\n");
return -ENOMEM;
@@ -201,7 +201,7 @@ void piix4_sb800_region_release(struct device *dev, struct sb800_mmio_cfg *mmio_
{
if (mmio_cfg->use_mmio) {
iounmap(mmio_cfg->addr);
- release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
+ release_mem_region(FCH_PM_BASE,
SB800_PIIX4_FCH_PM_SIZE);
return;
}
--
2.43.0
next prev parent reply other threads:[~2025-04-15 0:27 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 0:26 [PATCH v4 0/5] AMD Zen debugging documentation Mario Limonciello
2025-04-15 0:26 ` [PATCH v4 1/5] Documentation: Add AMD Zen debugging document Mario Limonciello
2025-04-15 0:26 ` [PATCH v4 2/5] i2c: piix4: Depends on X86 Mario Limonciello
2025-04-17 22:16 ` Andi Shyti
2025-04-17 22:21 ` Mario Limonciello
2025-04-15 0:26 ` Mario Limonciello [this message]
2025-04-15 0:26 ` [PATCH v4 4/5] platform/x86/amd: pmc: use FCH_PM_BASE definition Mario Limonciello
2025-04-15 15:13 ` Yazen Ghannam
2025-04-15 15:45 ` Mario Limonciello
2025-04-16 7:58 ` Ingo Molnar
2025-04-16 13:44 ` Yazen Ghannam
2025-04-15 0:26 ` [PATCH v4 5/5] x86/CPU/AMD: Print the reason for the last reset Mario Limonciello
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