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[209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c92770d42bsi1187033485a.381.2025.04.22.19.57.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Apr 2025 19:57:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7QIV-0007Bt-2A; Tue, 22 Apr 2025 22:57:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7QIL-0007Ax-9c; Tue, 22 Apr 2025 22:57:05 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7QIH-00043I-Vl; Tue, 22 Apr 2025 22:57:05 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 23 Apr 2025 10:56:51 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Wed, 23 Apr 2025 10:56:51 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v3 0/3] hw/misc/aspeed_otp: Introduce OTP memory and integrate with SBC Date: Wed, 23 Apr 2025 10:56:48 +0800 Message-ID: <20250423025651.189702-1-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 4TMU2/7/wdpn From: Kane-Chen-AS Dear reviewers, This patch series introduces a new model for the ASPEED OTP (One-Time Programmable) memory and integrates it with the ASPEED Secure Boot Controller (SBC) and SoC models such as AST1030 and AST2600. The OTP memory is implemented as a QEMU device (`aspeed.otpmem`) and is designed to simulate fuse-like behavior using a block backend. Programming is restricted by irreversible bit-flip rules (e.g., 0->1 or 1->0 depending on address parity). The memory content is persistent and can be passed via `-drive id=otpmem`. The SBC device (`aspeed.sbc`) accesses the OTP device through a QOM link property. This decouples OTP handling from the SBC logic and allows future extensibility such as secure configuration or key provisioning. The SoC integration connects the OTP memory to the SBC and provides device-tree-style infrastructure for future firmware use. Any feedback or suggestions are appreciated! Thanks, Kane --- ChangeLog --------- v3: - Minor fixes and refinements on top of v2 content v2: - Separated the OTP memory into a standalone QEMU device (`aspeed.otpmem`) - Replaced ad-hoc file handling with standard `-drive` backend integration - Linked OTP to SBC via QOM property for cleaner abstraction - Improved memory bounds checking and irreversible programming logic v1: - Embedded OTP logic in the SBC model and created the backing file internally. --- Kane-Chen-AS (3): hw/misc/aspeed_otp: Add Aspeed OTP memory device model hw/misc/aspeed_sbc: Connect Aspeed OTP memory device to SBC controller hw/arm: Integrate Aspeed OTP memory into AST10x0 and AST2600 SoCs hw/arm/aspeed_ast10x0.c | 19 +++ hw/arm/aspeed_ast2600.c | 19 +++ hw/misc/aspeed_otpmem.c | 211 ++++++++++++++++++++++++++++++++ hw/misc/aspeed_sbc.c | 146 ++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/arm/aspeed_soc.h | 2 + include/hw/misc/aspeed_otpmem.h | 40 ++++++ include/hw/misc/aspeed_sbc.h | 15 +++ 8 files changed, 453 insertions(+) create mode 100644 hw/misc/aspeed_otpmem.c create mode 100644 include/hw/misc/aspeed_otpmem.h -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7421BC369C2 for ; Wed, 23 Apr 2025 02:58:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7QIX-0007Db-Cb; Tue, 22 Apr 2025 22:57:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7QIL-0007Ax-9c; Tue, 22 Apr 2025 22:57:05 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7QIH-00043I-Vl; Tue, 22 Apr 2025 22:57:05 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 23 Apr 2025 10:56:51 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Wed, 23 Apr 2025 10:56:51 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v3 0/3] hw/misc/aspeed_otp: Introduce OTP memory and integrate with SBC Date: Wed, 23 Apr 2025 10:56:48 +0800 Message-ID: <20250423025651.189702-1-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kane-Chen-AS Dear reviewers, This patch series introduces a new model for the ASPEED OTP (One-Time Programmable) memory and integrates it with the ASPEED Secure Boot Controller (SBC) and SoC models such as AST1030 and AST2600. The OTP memory is implemented as a QEMU device (`aspeed.otpmem`) and is designed to simulate fuse-like behavior using a block backend. Programming is restricted by irreversible bit-flip rules (e.g., 0->1 or 1->0 depending on address parity). The memory content is persistent and can be passed via `-drive id=otpmem`. The SBC device (`aspeed.sbc`) accesses the OTP device through a QOM link property. This decouples OTP handling from the SBC logic and allows future extensibility such as secure configuration or key provisioning. The SoC integration connects the OTP memory to the SBC and provides device-tree-style infrastructure for future firmware use. Any feedback or suggestions are appreciated! Thanks, Kane --- ChangeLog --------- v3: - Minor fixes and refinements on top of v2 content v2: - Separated the OTP memory into a standalone QEMU device (`aspeed.otpmem`) - Replaced ad-hoc file handling with standard `-drive` backend integration - Linked OTP to SBC via QOM property for cleaner abstraction - Improved memory bounds checking and irreversible programming logic v1: - Embedded OTP logic in the SBC model and created the backing file internally. --- Kane-Chen-AS (3): hw/misc/aspeed_otp: Add Aspeed OTP memory device model hw/misc/aspeed_sbc: Connect Aspeed OTP memory device to SBC controller hw/arm: Integrate Aspeed OTP memory into AST10x0 and AST2600 SoCs hw/arm/aspeed_ast10x0.c | 19 +++ hw/arm/aspeed_ast2600.c | 19 +++ hw/misc/aspeed_otpmem.c | 211 ++++++++++++++++++++++++++++++++ hw/misc/aspeed_sbc.c | 146 ++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/arm/aspeed_soc.h | 2 + include/hw/misc/aspeed_otpmem.h | 40 ++++++ include/hw/misc/aspeed_sbc.h | 15 +++ 8 files changed, 453 insertions(+) create mode 100644 hw/misc/aspeed_otpmem.c create mode 100644 include/hw/misc/aspeed_otpmem.h -- 2.43.0