From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-44.mimecast.com (us-smtp-delivery-44.mimecast.com [205.139.111.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C6CB1EBFEB for ; Wed, 23 Apr 2025 21:45:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.139.111.44 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745444704; cv=none; b=bU7KtGjGZjR7KYqH9Ev3J1EDdwSVK2Etu19QpFl0gmE/lwukgHItIcUTfFGI6GaM8QkToMeXtyiMlrYrxOynWRdW0ZxsWRQSKqkP/vwA7RYsUjgfIWIRACW1R/IAj2UQYae9CiK2Ht2dqNX4+NC0UvgaBe57Ci0s+HBZIcXwAFM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745444704; c=relaxed/simple; bh=cwPSFGZCGQgYUz3qEcOtcFPBuD80brv7+/UaXLNSHm8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:content-type; b=Xuy70o+yVoz8qhpmVppsqkn/83ANfgW1Siw+besJ10a54X96eJRx3hzU4CUxv8UVc789sIQXjAND8x+pl7RbAY4gJca9heN2zqNeuZYUYPxHNMJCnaLq2mNAOFCwggFgv3CUHpkRxxbnttIHM/bkv9LbLs5dQ9EYI745Zhdiuv0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com; spf=fail smtp.mailfrom=gmail.com; arc=none smtp.client-ip=205.139.111.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=gmail.com Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-272-WPrkCWAuMLSumlBMeXytRA-1; Wed, 23 Apr 2025 17:43:41 -0400 X-MC-Unique: WPrkCWAuMLSumlBMeXytRA-1 X-Mimecast-MFC-AGG-ID: WPrkCWAuMLSumlBMeXytRA_1745444620 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id D93E3180010A; Wed, 23 Apr 2025 21:43:39 +0000 (UTC) Received: from dreadlord.redhat.com (unknown [10.64.136.98]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A19B219560A3; Wed, 23 Apr 2025 21:43:37 +0000 (UTC) From: Dave Airlie To: dri-devel@lists.freedesktop.org, tj@kernel.org, christian.koenig@amd.com Cc: cgroups@vger.kernel.org Subject: [PATCH 4/5] amdgpu: add support for memcg integration Date: Thu, 24 Apr 2025 07:37:06 +1000 Message-ID: <20250423214321.100440-5-airlied@gmail.com> In-Reply-To: <20250423214321.100440-1-airlied@gmail.com> References: <20250423214321.100440-1-airlied@gmail.com> Precedence: bulk X-Mailing-List: cgroups@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: 1xB4GAIvgeeQhA_oGovs_McprAP6w4LaAtUD_9YqS74_1745444620 X-Mimecast-Originator: gmail.com Content-Transfer-Encoding: quoted-printable content-type: text/plain; charset=WINDOWS-1252; x-default=true From: Dave Airlie This adds the memcg object for any user allocated object, and adds account_op to necessary paths which might populate a tt object. Signed-off-by: Dave Airlie --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 14 +++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 + 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_cs.c index 82df06a72ee0..1a275224b4a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -787,6 +787,7 @@ static int amdgpu_cs_bo_validate(void *param, struct am= dgpu_bo *bo) =09struct ttm_operation_ctx ctx =3D { =09=09.interruptible =3D true, =09=09.no_wait_gpu =3D false, +=09=09.account_op =3D true, =09=09.resv =3D bo->tbo.base.resv =09}; =09uint32_t domain; @@ -839,7 +840,11 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parse= r *p, =09=09=09=09union drm_amdgpu_cs *cs) { =09struct amdgpu_fpriv *fpriv =3D p->filp->driver_priv; -=09struct ttm_operation_ctx ctx =3D { true, false }; +=09struct ttm_operation_ctx ctx =3D { +=09=09.interruptible =3D true, +=09=09.no_wait_gpu =3D false, +=09=09.account_op =3D true, +=09}; =09struct amdgpu_vm *vm =3D &fpriv->vm; =09struct amdgpu_bo_list_entry *e; =09struct drm_gem_object *obj; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gem.c index 69429df09477..bdad9a862ed3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -89,6 +89,7 @@ static void amdgpu_gem_object_free(struct drm_gem_object = *gobj) =09struct amdgpu_bo *aobj =3D gem_to_amdgpu_bo(gobj); =20 =09amdgpu_hmm_unregister(aobj); +=09mem_cgroup_put(aobj->tbo.memcg); =09ttm_bo_put(&aobj->tbo); } =20 @@ -116,6 +117,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev= , unsigned long size, =09bp.domain =3D initial_domain; =09bp.bo_ptr_size =3D sizeof(struct amdgpu_bo); =09bp.xcp_id_plus1 =3D xcp_id_plus1; +=09bp.memcg =3D get_mem_cgroup_from_mm(current->mm); =20 =09r =3D amdgpu_bo_create_user(adev, &bp, &ubo); =09if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 0b9987781f76..777cf05ebac8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -632,6 +632,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, =09struct ttm_operation_ctx ctx =3D { =09=09.interruptible =3D (bp->type !=3D ttm_bo_type_kernel), =09=09.no_wait_gpu =3D bp->no_wait_gpu, +=09=09.account_op =3D true, =09=09/* We opt to avoid OOM on system pages allocations */ =09=09.gfp_retry_mayfail =3D true, =09=09.allow_res_evict =3D bp->type !=3D ttm_bo_type_kernel, @@ -657,16 +658,21 @@ int amdgpu_bo_create(struct amdgpu_device *adev, =09=09size =3D ALIGN(size, PAGE_SIZE); =09} =20 -=09if (!amdgpu_bo_validate_size(adev, size, bp->domain)) +=09if (!amdgpu_bo_validate_size(adev, size, bp->domain)) { +=09=09mem_cgroup_put(bp->memcg); =09=09return -ENOMEM; +=09} =20 =09BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); =20 =09*bo_ptr =3D NULL; =09bo =3D kvzalloc(bp->bo_ptr_size, GFP_KERNEL); -=09if (bo =3D=3D NULL) +=09if (bo =3D=3D NULL) { +=09=09mem_cgroup_put(bp->memcg); =09=09return -ENOMEM; +=09} =09drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); +=09bo->tbo.memcg =3D bp->memcg; =09bo->tbo.base.funcs =3D &amdgpu_gem_object_funcs; =09bo->vm_bo =3D NULL; =09bo->preferred_domains =3D bp->preferred_domain ? bp->preferred_domain : @@ -1341,7 +1347,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) { =09struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->bdev); -=09struct ttm_operation_ctx ctx =3D { false, false }; +=09struct ttm_operation_ctx ctx =3D { .interruptible =3D false, +=09=09=09=09=09 .no_wait_gpu =3D false, +=09=09=09=09=09 .account_op =3D true }; =09struct amdgpu_bo *abo =3D ttm_to_amdgpu_bo(bo); =09int r; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.h index 375448627f7b..9a4c506cfb76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -55,6 +55,7 @@ struct amdgpu_bo_param { =09enum ttm_bo_type=09=09type; =09bool=09=09=09=09no_wait_gpu; =09struct dma_resv=09=09=09*resv; +=09struct mem_cgroup *memcg; =09void=09=09=09=09(*destroy)(struct ttm_buffer_object *bo); =09/* xcp partition number plus 1, 0 means any partition */ =09int8_t=09=09=09=09xcp_id_plus1; --=20 2.49.0