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Fri, 25 Apr 2025 09:43:12 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::f716]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e5d264sm2871271f8f.95.2025.04.25.09.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 09:43:12 -0700 (PDT) Date: Fri, 25 Apr 2025 18:43:11 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong Message-ID: <20250425-14cba750e7a8932b576b69d9@orel> References: <20250425160203.2774835-1-dbarboza@ventanamicro.com> <20250425160203.2774835-9-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250425160203.2774835-9-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Fri, Apr 25, 2025 at 01:02:02PM -0300, Daniel Henrique Barboza wrote: > We want to support scounteren as a KVM CSR. The KVM UAPI defines every > CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. > > The other existing cases where the property size does not match the KVM > reg size happens with uint64_t properties, like 'mstatus'. When running > a 32 bit CPU we'll write a 32 bit 'sstatus' KVM reg into the 64 bit > 'mstatus' field. As long as we're consistent, i.e. we're always > reading/writing the same words, this is ok. > > For scounteren, a KVM guest running in a 64 bit CPU will end up writing > a 64 bit reg in a 32 bit field. This will have all sort of funny side > effects in the KVM guest that we would rather avoid. > > Increase scounteren to target_ulong to allow KVM to read/write the > scounteren CSR without any surprises. > > Aside from bumping the version of the RISCVCPU vmstate no other > behavioral changes are expected. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.h | 9 ++++++++- > target/riscv/machine.c | 6 +++--- > 2 files changed, 11 insertions(+), 4 deletions(-) > Reviewed-by: Andrew Jones