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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
	palmer@rivosinc.com, ajones@ventanamicro.com,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 7/9] target/riscv/kvm: add senvcfg CSR
Date: Fri, 25 Apr 2025 08:37:03 -0300	[thread overview]
Message-ID: <20250425113705.2741457-8-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20250425113705.2741457-1-dbarboza@ventanamicro.com>

We're missing the senvcfg CSRs which is already present in the
KVM UAPI.

Reported-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/kvm/kvm-cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index f341085ba1..e37fa38c07 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -249,6 +249,7 @@ static KVMCPUConfig kvm_csr_cfgs[] = {
     KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)),
     KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)),
     KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)),
+    KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)),
 };
 
 static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg)
@@ -698,6 +699,7 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env)
     env->stval = 0;
     env->mip = 0;
     env->satp = 0;
+    env->senvcfg = 0;
 }
 
 static int kvm_riscv_get_regs_fp(CPUState *cs)
-- 
2.49.0



  parent reply	other threads:[~2025-04-25 11:42 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-25 11:36 [PATCH v2 0/9] target/riscv/kvm: CSR related fixes Daniel Henrique Barboza
2025-04-25 11:36 ` [PATCH v2 1/9] target/riscv/kvm: minor fixes/tweaks Daniel Henrique Barboza
2025-04-25 11:43   ` Andrew Jones
2025-04-25 11:36 ` [PATCH v2 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg() Daniel Henrique Barboza
2025-04-25 11:44   ` Andrew Jones
2025-04-25 11:36 ` [PATCH v2 3/9] target/riscv/kvm: turn u32/u64 reg functions in macros Daniel Henrique Barboza
2025-04-25 11:45   ` Andrew Jones
2025-04-25 11:37 ` [PATCH v2 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro Daniel Henrique Barboza
2025-04-25 11:48   ` Andrew Jones
2025-04-25 11:37 ` [PATCH v2 5/9] target/riscv/kvm: add kvm_csr_cfgs[] Daniel Henrique Barboza
2025-04-25 11:58   ` Andrew Jones
2025-04-25 11:37 ` [PATCH v2 6/9] target/riscv/kvm: do not read unavailable CSRs Daniel Henrique Barboza
2025-04-25 12:02   ` Andrew Jones
2025-04-25 11:37 ` Daniel Henrique Barboza [this message]
2025-04-25 12:03   ` [PATCH v2 7/9] target/riscv/kvm: add senvcfg CSR Andrew Jones
2025-04-25 11:37 ` [PATCH v2 8/9] target/riscv: widen (m|s)counteren to target_ulong Daniel Henrique Barboza
2025-04-25 12:11   ` Andrew Jones
2025-04-25 13:10     ` Daniel Henrique Barboza
2025-04-25 11:37 ` [PATCH v2 9/9] target/riscv/kvm: add scounteren CSR Daniel Henrique Barboza
2025-04-25 12:12   ` Andrew Jones

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