From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: u-boot@lists.denx.de
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
Tom Rini <trini@konsulko.com>
Subject: [PATCH] riscv: insn-def.h: Fix header guard
Date: Mon, 28 Apr 2025 04:48:45 +0000 [thread overview]
Message-ID: <20250428044848.1132018-1-mchitale@ventanamicro.com> (raw)
Fix the erroneous header guard for insn-def.h to reflect the correct
header name.
Fixes: bfc8ca3f7f6 ("riscv: Add support for defining instructions")
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
arch/riscv/include/asm/insn-def.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
index 19a10cad84c..1869342b167 100644
--- a/arch/riscv/include/asm/insn-def.h
+++ b/arch/riscv/include/asm/insn-def.h
@@ -5,8 +5,8 @@
* Ported from linux insn-def.h.
*/
-#ifndef _ASM_RISCV_BARRIER_H
-#define _ASM_RISCV_BARRIER_H
+#ifndef _ASM_RISCV_INSN_DEF_H
+#define _ASM_RISCV_INSN_DEF_H
#define INSN_I_SIMM12_SHIFT 20
#define INSN_I_RS1_SHIFT 15
@@ -36,4 +36,4 @@
__INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
RV_##rs1, RV_##simm12)
-#endif /* _ASM_RISCV_BARRIER_H */
+#endif /* _ASM_RISCV_INSN_DEF_H */
--
2.43.0
next reply other threads:[~2025-04-28 4:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-28 4:48 Mayuresh Chitale [this message]
2025-05-08 7:29 ` [PATCH] riscv: insn-def.h: Fix header guard Leo Liang
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