Re: [PATCH] coresight: trbe: Save/restore state across CPU low power state

[Leo Yan <leo.yan@arm.com>]

On Mon, Apr 28, 2025 at 01:55:29PM +0100, Mike Leach wrote:

[...]

> > > The TRBE PM can follow the model of the ETE / ETMv4 and save and
> > > restore if currently in use.
> >
> > If TRBE PM is registered as a seperate PM notifier, a prominent issue is
> > it cannot promise the depedency between ETE and TRBE when execute CPU
> > power management.  E.g., when entering CPU idle states, ETE should be
> > disabled prior to switch off TRBE, otherwise, it might cause lockup
> > issue in hardware.  If ETE and TRBE register PM notifier separately,
> > we cannot ensure the sequence between ETE and TRBE, this is why we need
> > to do the operations based on CoreSight paths.
> >
> 
> I believe that the architecture requires that if the disabled TRBE
> cannot receive trace then the ETE should regard the trace as having
> been output (A1.4 ETE spec). Incorrect sequencing should only result
> in missing trace, not a core lockup - unless the implementation is not
> compliant.

Thanks for clarification, Mike.

I would prefer to stick with the CoreSight path approach, as this will
help us to resolve the issue in a general way - not just for ETE / TRBE
case, this would be applicable for other types of links and sinks.

Thanks,
Leo