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Tsirkin" , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v5 09/11] qtest/libqos/pci: Enforce balanced iomap/unmap Date: Fri, 2 May 2025 13:04:43 +1000 Message-ID: <20250502030446.88310-10-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250502030446.88310-1-npiggin@gmail.com> References: <20250502030446.88310-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=npiggin@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add assertions to ensure a BAR is not mapped twice, and that only previously mapped BARs are unmapped. This can help catch bugs and fragile coding. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Reviewed-by: Akihiko Odaki Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.h | 9 +++++++ tests/qtest/libqos/pci.c | 51 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 19f1dd13501..a51bf60620f 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -60,10 +60,19 @@ struct QPCIBar { bool is_io; }; +/* + * hw/pci permits 7 (PCI_NUM_REGIONS) regions, the last for PCI_ROM_SLOT. + * libqos does not implement PCI_ROM_SLOT at the moment, and as such it + * permits 6. + */ +#define QPCI_NUM_REGIONS 6 + struct QPCIDevice { QPCIBus *bus; int devfn; + bool bars_mapped[QPCI_NUM_REGIONS]; + QPCIBar bars[QPCI_NUM_REGIONS]; bool msix_enabled; QPCIBar msix_table_bar, msix_pba_bar; uint64_t msix_table_off, msix_pba_off; diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index de95329e486..694f1458f46 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -79,12 +79,17 @@ QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn) void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr) { uint16_t vendor_id, device_id; + int i; qpci_device_set(dev, bus, addr->devfn); vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); device_id = qpci_config_readw(dev, PCI_DEVICE_ID); g_assert(!addr->vendor_id || vendor_id == addr->vendor_id); g_assert(!addr->device_id || device_id == addr->device_id); + + for (i = 0; i < QPCI_NUM_REGIONS; i++) { + g_assert(!dev->bars_mapped[i]); + } } static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev) @@ -549,21 +554,31 @@ void qpci_memwrite(QPCIDevice *dev, QPCIBar token, uint64_t off, dev->bus->memwrite(dev->bus, token.addr + off, buf, len); } -QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr) +static uint8_t qpci_bar_reg(int barno) { - QPCIBus *bus = dev->bus; static const int bar_reg_map[] = { PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5, }; + + g_assert(barno >= 0 && barno <= QPCI_NUM_REGIONS); + + return bar_reg_map[barno]; +} + +QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr) +{ + QPCIBus *bus = dev->bus; QPCIBar bar; int bar_reg; uint32_t addr, size; uint32_t io_type; uint64_t loc; - g_assert(barno >= 0 && barno <= 5); - bar_reg = bar_reg_map[barno]; + g_assert(barno >= 0 && barno <= QPCI_NUM_REGIONS); + g_assert(!dev->bars_mapped[barno]); + + bar_reg = qpci_bar_reg(barno); qpci_config_writel(dev, bar_reg, 0xFFFFFFFF); addr = qpci_config_readl(dev, bar_reg); @@ -606,12 +621,34 @@ QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr) } bar.addr = loc; + + dev->bars_mapped[barno] = true; + dev->bars[barno] = bar; + return bar; } void qpci_iounmap(QPCIDevice *dev, QPCIBar bar) { - /* FIXME */ + int bar_reg; + int i; + + g_assert(bar.addr); + + for (i = 0; i < QPCI_NUM_REGIONS; i++) { + if (!dev->bars_mapped[i]) { + continue; + } + if (dev->bars[i].addr == bar.addr) { + dev->bars_mapped[i] = false; + memset(&dev->bars_mapped[i], 0, sizeof(dev->bars_mapped[i])); + bar_reg = qpci_bar_reg(i); + qpci_config_writel(dev, bar_reg, 0xFFFFFFFF); + /* FIXME: the address space is leaked */ + return; + } + } + g_assert_not_reached(); /* device was not iomap()ed */ } QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr) @@ -622,6 +659,10 @@ QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr) void qpci_migrate_fixup(QPCIDevice *to, QPCIDevice *from) { + memcpy(to->bars_mapped, from->bars_mapped, sizeof(from->bars_mapped)); + memset(from->bars_mapped, 0, sizeof(from->bars_mapped)); + memcpy(to->bars, from->bars, sizeof(from->bars)); + memset(from->bars, 0, sizeof(from->bars)); } void add_qpci_address(QOSGraphEdgeOptions *opts, QPCIAddress *addr) -- 2.47.1