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5 May 2025 22:55:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746485734; bh=5Ul5afnxT4Ev7pMFKXsZJc0l/RU9J+GqH7JwLx6dk74=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NlTI5LR6js7dFUd1BpHxTagrwpqA0FOQnRhcrHodC3qEI/p24tpXoxDxg4IzF1xvn 3WvN5JwfAFX9sVxWHWMFNEhIUqCvOXk6QbIpwn+X6JxNDp3+lzNx03JJnTXzV1QEGP VIbZlorf3gAhYD91wvn1V0L5Mv2/YGrmI522vP/k10E5UC9UGjr2Fhixa05/0HktD9 3N/UiDXS8wvFhnMY/CuJx+l7tWi2fVKxZYO1sXmsnr3UEcmBvUsQt3UTdo2xDg7e1E GESMTG8+RJa81RVgcrFrLX58egX8NrdZCi7Bpk7xZWgFO0duAphjKJIpiHMYghpzdX iMu5xrUbUQhgw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Vladimir Kondratiev , Thomas Gleixner , Anup Patel , Sasha Levin , paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org Subject: [PATCH AUTOSEL 6.12 451/486] irqchip/riscv-aplic: Add support for hart indexes Date: Mon, 5 May 2025 18:38:47 -0400 Message-Id: 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MmE0OGNjIF0KClJJU0MtViBBUExJQyBzcGVjaWZpY2F0aW9uIGRlZmluZXMgImhhcnQgaW5kZXgi IGluOgoKICBodHRwczovL2dpdGh1Yi5jb20vcmlzY3YvcmlzY3YtYWlhCgpXaXRoaW4gYSBnaXZl biBpbnRlcnJ1cHQgZG9tYWluLCBlYWNoIG9mIHRoZSBkb21haW7igJlzIGhhcnRzIGhhcyBhIHVu aXF1ZQppbmRleCBudW1iZXIgaW4gdGhlIHJhbmdlIDAgdG8gMl4xNCDiiJIgMSAoPSAxNiwzODMp LiBUaGUgaW5kZXggbnVtYmVyIGEKZG9tYWluIGFzc29jaWF0ZXMgd2l0aCBhIGhhcnQgbWF5IG9y IG1heSBub3QgaGF2ZSBhbnkgcmVsYXRpb25zaGlwIHRvIHRoZQp1bmlxdWUgaGFydCBpZGVudGlm aWVyICjigJxoYXJ0IElE4oCdKSB0aGF0IHRoZSBSSVNDLVYgUHJpdmlsZWdlZCBBcmNoaXRlY3R1 cmUKYXNzaWducyB0byB0aGUgaGFydC4gVHdvIGRpZmZlcmVudCBpbnRlcnJ1cHQgZG9tYWlucyBt YXkgZW1wbG95IGVudGlyZWx5CmRpZmZlcmVudCBpbmRleCBudW1iZXJzIGZvciB0aGUgc2FtZSBz ZXQgb2YgaGFydHMuCgpGdXJ0aGVyLCB0aGlzIGRvY3VtZW50IHNheXMgaW4gIjQuNSBNZW1vcnkt bWFwcGVkIGNvbnRyb2wgcmVnaW9uIGZvciBhbgppbnRlcnJ1cHQgZG9tYWluIjoKClRoZSBhcnJh eSBvZiBJREMgc3RydWN0dXJlcyBtYXkgaW5jbHVkZSBzb21lIGZvciBwb3RlbnRpYWwgaGFydCBp bmRleApudW1iZXJzIHRoYXQgYXJlIG5vdCBhY3R1YWwgaGFydCBpbmRleCBudW1iZXJzIGluIHRo ZSBkb21haW4uIEZvciBleGFtcGxlLAp0aGUgZmlyc3QgSURDIHN0cnVjdHVyZSBpcyBhbHdheXMg Zm9yIGhhcnQgaW5kZXggMCwgYnV0IDAgaXMgbm90Cm5lY2Vzc2FyaWx5IGEgdmFsaWQgaW5kZXgg bnVtYmVyIGZvciBhbnkgaGFydCBpbiB0aGUgZG9tYWluLgoKU3VwcG9ydCBhcmJpdHJhcnkgaGFy dCBpbmRpY2VzIHNwZWNpZmllZCBpbiBhbiBvcHRpb25hbCBBUExJQyBwcm9wZXJ0eQoicmlzY3Ys aGFydC1pbmRleGVzIiB3aGljaCBpcyBzcGVjaWZpZWQgYXMgYW4gYXJyYXkgb2YgdTMyIGVsZW1l bnRzLCBvbmUKcGVyIGludGVycnVwdCB0YXJnZXQuIElmIHRoaXMgcHJvcGVydHkgaXMgbm90IHNw ZWNpZmllZCwgZmFsbGJhY2sgdG8gdXNlCmxvZ2ljYWwgaGFydCBpbmRpY2VzIHdpdGhpbiB0aGUg ZG9tYWluLgoKU2lnbmVkLW9mZi1ieTogVmxhZGltaXIgS29uZHJhdGlldiA8dmxhZGltaXIua29u ZHJhdGlldkBtb2JpbGV5ZS5jb20+ClNpZ25lZC1vZmYtYnk6IFRob21hcyBHbGVpeG5lciA8dGds eEBsaW51dHJvbml4LmRlPgpSZXZpZXdlZC1ieTogQW51cCBQYXRlbCA8YW51cEBicmFpbmZhdWx0 Lm9yZz4KTGluazogaHR0cHM6Ly9sb3JlLmtlcm5lbC5vcmcvYWxsLzIwMjUwMTI5MDkxNjM3LjE2 NjcyNzktMy12bGFkaW1pci5rb25kcmF0aWV2QG1vYmlsZXllLmNvbQpTaWduZWQtb2ZmLWJ5OiBT YXNoYSBMZXZpbiA8c2FzaGFsQGtlcm5lbC5vcmc+Ci0tLQogZHJpdmVycy9pcnFjaGlwL2lycS1y aXNjdi1hcGxpYy1kaXJlY3QuYyB8IDI0ICsrKysrKysrKysrKysrKysrKysrKy0tLQogMSBmaWxl IGNoYW5nZWQsIDIxIGluc2VydGlvbnMoKyksIDMgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEv ZHJpdmVycy9pcnFjaGlwL2lycS1yaXNjdi1hcGxpYy1kaXJlY3QuYyBiL2RyaXZlcnMvaXJxY2hp cC9pcnEtcmlzY3YtYXBsaWMtZGlyZWN0LmMKaW5kZXggN2NkNmI2NDY3NzRiOS4uMjA1YWQ2MWQx NWU0OSAxMDA2NDQKLS0tIGEvZHJpdmVycy9pcnFjaGlwL2lycS1yaXNjdi1hcGxpYy1kaXJlY3Qu YworKysgYi9kcml2ZXJzL2lycWNoaXAvaXJxLXJpc2N2LWFwbGljLWRpcmVjdC5jCkBAIC0zMSw3 ICszMSw3IEBAIHN0cnVjdCBhcGxpY19kaXJlY3QgewogfTsKIAogc3RydWN0IGFwbGljX2lkYyB7 Ci0JdW5zaWduZWQgaW50CQloYXJ0X2luZGV4OworCXUzMgkJCWhhcnRfaW5kZXg7CiAJdm9pZCBf X2lvbWVtCQkqcmVnczsKIAlzdHJ1Y3QgYXBsaWNfZGlyZWN0CSpkaXJlY3Q7CiB9OwpAQCAtMjE5 LDYgKzIxOSwyMCBAQCBzdGF0aWMgaW50IGFwbGljX2RpcmVjdF9wYXJzZV9wYXJlbnRfaHdpcnEo c3RydWN0IGRldmljZSAqZGV2LCB1MzIgaW5kZXgsCiAJcmV0dXJuIDA7CiB9CiAKK3N0YXRpYyBp bnQgYXBsaWNfZGlyZWN0X2dldF9oYXJ0X2luZGV4KHN0cnVjdCBkZXZpY2UgKmRldiwgdTMyIGxv Z2ljYWxfaW5kZXgsCisJCQkJICAgICAgIHUzMiAqaGFydF9pbmRleCkKK3sKKwljb25zdCBjaGFy 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smtp.kernel.org (Postfix) with ESMTPSA id 2535DC4CEE4; Mon, 5 May 2025 22:55:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746485734; bh=5Ul5afnxT4Ev7pMFKXsZJc0l/RU9J+GqH7JwLx6dk74=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NlTI5LR6js7dFUd1BpHxTagrwpqA0FOQnRhcrHodC3qEI/p24tpXoxDxg4IzF1xvn 3WvN5JwfAFX9sVxWHWMFNEhIUqCvOXk6QbIpwn+X6JxNDp3+lzNx03JJnTXzV1QEGP VIbZlorf3gAhYD91wvn1V0L5Mv2/YGrmI522vP/k10E5UC9UGjr2Fhixa05/0HktD9 3N/UiDXS8wvFhnMY/CuJx+l7tWi2fVKxZYO1sXmsnr3UEcmBvUsQt3UTdo2xDg7e1E GESMTG8+RJa81RVgcrFrLX58egX8NrdZCi7Bpk7xZWgFO0duAphjKJIpiHMYghpzdX iMu5xrUbUQhgw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Vladimir Kondratiev , Thomas Gleixner , Anup Patel , Sasha Levin , paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org Subject: [PATCH AUTOSEL 6.12 451/486] irqchip/riscv-aplic: Add support for hart indexes Date: Mon, 5 May 2025 18:38:47 -0400 Message-Id: <20250505223922.2682012-451-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org> References: <20250505223922.2682012-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.12.26 Content-Transfer-Encoding: 8bit From: Vladimir Kondratiev [ Upstream commit b93afe8a3ac53ae52296d65acfaa9c5f582a48cc ] RISC-V APLIC specification defines "hart index" in: https://github.com/riscv/riscv-aia Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, this document says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indices specified in an optional APLIC property "riscv,hart-indexes" which is specified as an array of u32 elements, one per interrupt target. If this property is not specified, fallback to use logical hart indices within the domain. Signed-off-by: Vladimir Kondratiev Signed-off-by: Thomas Gleixner Reviewed-by: Anup Patel Link: https://lore.kernel.org/all/20250129091637.1667279-3-vladimir.kondratiev@mobileye.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-riscv-aplic-direct.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c index 7cd6b646774b9..205ad61d15e49 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -31,7 +31,7 @@ struct aplic_direct { }; struct aplic_idc { - unsigned int hart_index; + u32 hart_index; void __iomem *regs; struct aplic_direct *direct; }; @@ -219,6 +219,20 @@ static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, return 0; } +static int aplic_direct_get_hart_index(struct device *dev, u32 logical_index, + u32 *hart_index) +{ + const char *prop_hart_index = "riscv,hart-indexes"; + struct device_node *np = to_of_node(dev->fwnode); + + if (!np || !of_property_present(np, prop_hart_index)) { + *hart_index = logical_index; + return 0; + } + + return of_property_read_u32_index(np, prop_hart_index, logical_index, hart_index); +} + int aplic_direct_setup(struct device *dev, void __iomem *regs) { int i, j, rc, cpu, current_cpu, setup_count = 0; @@ -265,8 +279,12 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) cpumask_set_cpu(cpu, &direct->lmask); idc = per_cpu_ptr(&aplic_idcs, cpu); - idc->hart_index = i; - idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + rc = aplic_direct_get_hart_index(dev, i, &idc->hart_index); + if (rc) { + dev_warn(dev, "hart index not found for IDC%d\n", i); + continue; + } + idc->regs = priv->regs + APLIC_IDC_BASE + idc->hart_index * APLIC_IDC_SIZE; idc->direct = direct; aplic_idc_set_delivery(idc, true); -- 2.39.5