[GIT PULL] ARM: socfpga: updates for v6.16

[Dinh Nguyen <dinguyen@kernel.org>]

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The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:

  Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_dts_updates_for_v6.16

for you to fetch changes up to 8dbffe5f5dd531a3c3f9d603462e499085449277:

  dt-bindings: clock: socfpga: convert to yaml (2025-05-03 13:33:23 -0500)

----------------------------------------------------------------
SoCFPGA DTS updates for v6.16
- Updates to dt-bindings
	- Document Agilex5 NAND daughter board
	- Convert Stratix10 FPGA Manager to json-schema
	- Convert Stratix10 Service Layer to json-schema
	- Add document for Terasic's DE10-nano board
- Add support for Agilex5 NAND daughter board
- Add basic support for Terasic's DE10-nano board

----------------------------------------------------------------
Mahesh Rao (2):
      dt-bindings: fpga: stratix10: Convert to json-schema
      dt-bindings: firmware: stratix10: Convert to json-schema

Matthew Gerlach (2):
      arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators
      dt-bindings: clock: socfpga: convert to yaml

Niravkumar L Rabara (6):
      dt-bindings: intel: document Agilex5 NAND daughter board
      arm64: dts: socfpga: agilex5: add NAND daughter board
      arm64: dts: socfpga: agilex5: fix gpio0 address
      arm64: dts: socfpga: agilex5: add qspi flash node
      arm64: dts: socfpga: agilex5: add led and memory nodes
      arm64: dts: socfpga: agilex: Add dma channel id for spi

Uwe Kleine-König (2):
      dt-bindings: altera: Add compatible for Terasic's DE10-nano
      ARM: dts: socfpga: Add basic support for Terrasic's de10-nano

 Documentation/devicetree/bindings/arm/altera.yaml  |   1 +
 .../bindings/arm/altera/socfpga-clk-manager.yaml   | 102 ++++++++++++++++++++-
 .../devicetree/bindings/arm/intel,socfpga.yaml     |   1 +
 .../devicetree/bindings/clock/altr_socfpga.txt     |  30 ------
 .../bindings/firmware/intel,stratix10-svc.txt      |  57 ------------
 .../bindings/firmware/intel,stratix10-svc.yaml     |  93 +++++++++++++++++++
 .../fpga/intel,stratix10-soc-fpga-mgr.yaml         |  36 ++++++++
 .../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt |  18 ----
 arch/arm/boot/dts/intel/socfpga/Makefile           |   1 +
 .../intel/socfpga/socfpga_cyclone5_de10nano.dts    |  95 +++++++++++++++++++
 arch/arm64/boot/dts/intel/Makefile                 |   1 +
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi      |   6 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi     |   4 +-
 .../arm64/boot/dts/intel/socfpga_agilex5_socdk.dts |  51 +++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk_nand.dts  |  89 ++++++++++++++++++
 15 files changed, 477 insertions(+), 108 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/altr_socfpga.txt
 delete mode 100644 Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
 create mode 100644 Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
 create mode 100644 Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
 delete mode 100644 Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts