From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Fuad Tabba <tabba@google.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Ben Horgan <ben.horgan@arm.com>
Subject: [PATCH v4 09/43] arm64: sysreg: Add registers trapped by HFG{R,W}TR2_EL2
Date: Tue, 6 May 2025 17:43:14 +0100 [thread overview]
Message-ID: <20250506164348.346001-10-maz@kernel.org> (raw)
In-Reply-To: <20250506164348.346001-1-maz@kernel.org>
Bulk addition of all the system registers trapped by HFG{R,W}TR2_EL2.
The descriptions are extracted from the BSD-licenced JSON file part
of the 2025-03 drop from ARM.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/tools/sysreg | 395 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 395 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index bb92464fc9abf..dc8f3134a451f 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2068,6 +2068,26 @@ Field 1 A
Field 0 M
EndSysreg
+Sysreg SCTLR_EL12 3 5 1 0 0
+Mapping SCTLR_EL1
+EndSysreg
+
+Sysreg SCTLRALIAS_EL1 3 0 1 4 6
+Mapping SCTLR_EL1
+EndSysreg
+
+Sysreg ACTLR_EL1 3 0 1 0 1
+Field 63:0 IMPDEF
+EndSysreg
+
+Sysreg ACTLR_EL12 3 5 1 0 1
+Mapping ACTLR_EL1
+EndSysreg
+
+Sysreg ACTLRALIAS_EL1 3 0 1 4 5
+Mapping ACTLR_EL1
+EndSysreg
+
Sysreg CPACR_EL1 3 0 1 0 2
Res0 63:32
Field 31 TCPAC
@@ -2083,6 +2103,323 @@ Field 17:16 ZEN
Res0 15:0
EndSysreg
+Sysreg CPACR_EL12 3 5 1 0 2
+Mapping CPACR_EL1
+EndSysreg
+
+Sysreg CPACRALIAS_EL1 3 0 1 4 4
+Mapping CPACR_EL1
+EndSysreg
+
+Sysreg ACTLRMASK_EL1 3 0 1 4 1
+Field 63:0 IMPDEF
+EndSysreg
+
+Sysreg ACTLRMASK_EL12 3 5 1 4 1
+Mapping ACTLRMASK_EL1
+EndSysreg
+
+Sysreg CPACRMASK_EL1 3 0 1 4 2
+Res0 63:32
+Field 31 TCPAC
+Field 30 TAM
+Field 29 E0POE
+Field 28 TTA
+Res0 27:25
+Field 24 SMEN
+Res0 23:21
+Field 20 FPEN
+Res0 19:17
+Field 16 ZEN
+Res0 15:0
+EndSysreg
+
+Sysreg CPACRMASK_EL12 3 5 1 4 2
+Mapping CPACRMASK_EL1
+EndSysreg
+
+Sysreg PFAR_EL1 3 0 6 0 5
+Field 63 NS
+Field 62 NSE
+Res0 61:56
+Field 55:52 PA_55_52
+Field 51:48 PA_51_48
+Field 47:0 PA
+EndSysreg
+
+Sysreg PFAR_EL12 3 5 6 0 5
+Mapping PFAR_EL1
+EndSysreg
+
+Sysreg RCWSMASK_EL1 3 0 13 0 3
+Field 63:0 RCWSMASK
+EndSysreg
+
+Sysreg SCTLR2_EL1 3 0 1 0 3
+Res0 63:13
+Field 12 CPTM0
+Field 11 CPTM
+Field 10 CPTA0
+Field 9 CPTA
+Field 8 EnPACM0
+Field 7 EnPACM
+Field 6 EnIDCP128
+Field 5 EASE
+Field 4 EnANERR
+Field 3 EnADERR
+Field 2 NMEA
+Res0 1:0
+EndSysreg
+
+Sysreg SCTLR2_EL12 3 5 1 0 3
+Mapping SCTLR2_EL1
+EndSysreg
+
+Sysreg SCTLR2ALIAS_EL1 3 0 1 4 7
+Mapping SCTLR2_EL1
+EndSysreg
+
+Sysreg SCTLR2MASK_EL1 3 0 1 4 3
+Res0 63:13
+Field 12 CPTM0
+Field 11 CPTM
+Field 10 CPTA0
+Field 9 CPTA
+Field 8 EnPACM0
+Field 7 EnPACM
+Field 6 EnIDCP128
+Field 5 EASE
+Field 4 EnANERR
+Field 3 EnADERR
+Field 2 NMEA
+Res0 1:0
+EndSysreg
+
+Sysreg SCTLR2MASK_EL12 3 5 1 4 3
+Mapping SCTLR2MASK_EL1
+EndSysreg
+
+Sysreg SCTLRMASK_EL1 3 0 1 4 0
+Field 63 TIDCP
+Field 62 SPINTMASK
+Field 61 NMI
+Field 60 EnTP2
+Field 59 TCSO
+Field 58 TCSO0
+Field 57 EPAN
+Field 56 EnALS
+Field 55 EnAS0
+Field 54 EnASR
+Field 53 TME
+Field 52 TME0
+Field 51 TMT
+Field 50 TMT0
+Res0 49:47
+Field 46 TWEDEL
+Field 45 TWEDEn
+Field 44 DSSBS
+Field 43 ATA
+Field 42 ATA0
+Res0 41
+Field 40 TCF
+Res0 39
+Field 38 TCF0
+Field 37 ITFSB
+Field 36 BT1
+Field 35 BT0
+Field 34 EnFPM
+Field 33 MSCEn
+Field 32 CMOW
+Field 31 EnIA
+Field 30 EnIB
+Field 29 LSMAOE
+Field 28 nTLSMD
+Field 27 EnDA
+Field 26 UCI
+Field 25 EE
+Field 24 E0E
+Field 23 SPAN
+Field 22 EIS
+Field 21 IESB
+Field 20 TSCXT
+Field 19 WXN
+Field 18 nTWE
+Res0 17
+Field 16 nTWI
+Field 15 UCT
+Field 14 DZE
+Field 13 EnDB
+Field 12 I
+Field 11 EOS
+Field 10 EnRCTX
+Field 9 UMA
+Field 8 SED
+Field 7 ITD
+Field 6 nAA
+Field 5 CP15BEN
+Field 4 SA0
+Field 3 SA
+Field 2 C
+Field 1 A
+Field 0 M
+EndSysreg
+
+Sysreg SCTLRMASK_EL12 3 5 1 4 0
+Mapping SCTLRMASK_EL1
+EndSysreg
+
+Sysreg TCR2MASK_EL1 3 0 2 7 3
+Res0 63:22
+Field 21 FNGNA1
+Field 20 FNGNA0
+Res0 19
+Field 18 FNG1
+Field 17 FNG0
+Field 16 A2
+Field 15 DisCH1
+Field 14 DisCH0
+Res0 13:12
+Field 11 HAFT
+Field 10 PTTWI
+Res0 9:6
+Field 5 D128
+Field 4 AIE
+Field 3 POE
+Field 2 E0POE
+Field 1 PIE
+Field 0 PnCH
+EndSysreg
+
+Sysreg TCR2MASK_EL12 3 5 2 7 3
+Mapping TCR2MASK_EL1
+EndSysreg
+
+Sysreg TCRMASK_EL1 3 0 2 7 2
+Res0 63:62
+Field 61 MTX1
+Field 60 MTX0
+Field 59 DS
+Field 58 TCMA1
+Field 57 TCMA0
+Field 56 E0PD1
+Field 55 E0PD0
+Field 54 NFD1
+Field 53 NFD0
+Field 52 TBID1
+Field 51 TBID0
+Field 50 HWU162
+Field 49 HWU161
+Field 48 HWU160
+Field 47 HWU159
+Field 46 HWU062
+Field 45 HWU061
+Field 44 HWU060
+Field 43 HWU059
+Field 42 HPD1
+Field 41 HPD0
+Field 40 HD
+Field 39 HA
+Field 38 TBI1
+Field 37 TBI0
+Field 36 AS
+Res0 35:33
+Field 32 IPS
+Res0 31
+Field 30 TG1
+Res0 29
+Field 28 SH1
+Res0 27
+Field 26 ORGN1
+Res0 25
+Field 24 IRGN1
+Field 23 EPD1
+Field 22 A1
+Res0 21:17
+Field 16 T1SZ
+Res0 15
+Field 14 TG0
+Res0 13
+Field 12 SH0
+Res0 11
+Field 10 ORGN0
+Res0 9
+Field 8 IRGN0
+Field 7 EPD0
+Res0 6:1
+Field 0 T0SZ
+EndSysreg
+
+Sysreg TCRMASK_EL12 3 5 2 7 2
+Mapping TCRMASK_EL1
+EndSysreg
+
+Sysreg ERXGSR_EL1 3 0 5 3 2
+Field 63 S63
+Field 62 S62
+Field 61 S61
+Field 60 S60
+Field 59 S59
+Field 58 S58
+Field 57 S57
+Field 56 S56
+Field 55 S55
+Field 54 S54
+Field 53 S53
+Field 52 S52
+Field 51 S51
+Field 50 S50
+Field 49 S49
+Field 48 S48
+Field 47 S47
+Field 46 S46
+Field 45 S45
+Field 44 S44
+Field 43 S43
+Field 42 S42
+Field 41 S41
+Field 40 S40
+Field 39 S39
+Field 38 S38
+Field 37 S37
+Field 36 S36
+Field 35 S35
+Field 34 S34
+Field 33 S33
+Field 32 S32
+Field 31 S31
+Field 30 S30
+Field 29 S29
+Field 28 S28
+Field 27 S27
+Field 26 S26
+Field 25 S25
+Field 24 S24
+Field 23 S23
+Field 22 S22
+Field 21 S21
+Field 20 S20
+Field 19 S19
+Field 18 S18
+Field 17 S17
+Field 16 S16
+Field 15 S15
+Field 14 S14
+Field 13 S13
+Field 12 S12
+Field 11 S11
+Field 10 S10
+Field 9 S9
+Field 8 S8
+Field 7 S7
+Field 6 S6
+Field 5 S5
+Field 4 S4
+Field 3 S3
+Field 2 S2
+Field 1 S1
+Field 0 S0
+EndSysreg
+
Sysreg TRFCR_EL1 3 0 1 2 1
Res0 63:7
UnsignedEnum 6:5 TS
@@ -3409,6 +3746,60 @@ Sysreg TTBR1_EL1 3 0 2 0 1
Fields TTBRx_EL1
EndSysreg
+Sysreg TCR_EL1 3 0 2 0 2
+Res0 63:62
+Field 61 MTX1
+Field 60 MTX0
+Field 59 DS
+Field 58 TCMA1
+Field 57 TCMA0
+Field 56 E0PD1
+Field 55 E0PD0
+Field 54 NFD1
+Field 53 NFD0
+Field 52 TBID1
+Field 51 TBID0
+Field 50 HWU162
+Field 49 HWU161
+Field 48 HWU160
+Field 47 HWU159
+Field 46 HWU062
+Field 45 HWU061
+Field 44 HWU060
+Field 43 HWU059
+Field 42 HPD1
+Field 41 HPD0
+Field 40 HD
+Field 39 HA
+Field 38 TBI1
+Field 37 TBI0
+Field 36 AS
+Res0 35
+Field 34:32 IPS
+Field 31:30 TG1
+Field 29:28 SH1
+Field 27:26 ORGN1
+Field 25:24 IRGN1
+Field 23 EPD1
+Field 22 A1
+Field 21:16 T1SZ
+Field 15:14 TG0
+Field 13:12 SH0
+Field 11:10 ORGN0
+Field 9:8 IRGN0
+Field 7 EPD0
+Res0 6
+Field 5:0 T0SZ
+EndSysreg
+
+Sysreg TCR_EL12 3 5 2 0 2
+Mapping TCR_EL1
+EndSysreg
+
+Sysreg TCRALIAS_EL1 3 0 2 7 6
+Mapping TCR_EL1
+EndSysreg
+
Sysreg TCR2_EL1 3 0 2 0 3
Res0 63:16
Field 15 DisCH1
@@ -3429,6 +3820,10 @@ Sysreg TCR2_EL12 3 5 2 0 3
Mapping TCR2_EL1
EndSysreg
+Sysreg TCR2ALIAS_EL1 3 0 2 7 7
+Mapping TCR2_EL1
+EndSysreg
+
Sysreg TCR2_EL2 3 4 2 0 3
Res0 63:16
Field 15 DisCH1
--
2.39.2
next prev parent reply other threads:[~2025-05-06 16:44 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-06 16:43 [PATCH v4 00/43] KVM: arm64: Revamp Fine Grained Trap handling Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 01/43] arm64: sysreg: Add ID_AA64ISAR1_EL1.LS64 encoding for FEAT_LS64WB Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 02/43] arm64: sysreg: Update ID_AA64MMFR4_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 03/43] arm64: sysreg: Add layout for HCR_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 04/43] arm64: sysreg: Replace HFGxTR_EL2 with HFG{R,W}TR_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 05/43] arm64: sysreg: Update ID_AA64PFR0_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 06/43] arm64: sysreg: Update PMSIDR_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 07/43] arm64: sysreg: Update TRBIDR_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 08/43] arm64: sysreg: Update CPACR_EL1 description Marc Zyngier
2025-05-06 16:43 ` Marc Zyngier [this message]
2025-05-06 16:43 ` [PATCH v4 10/43] arm64: sysreg: Add registers trapped by HDFG{R,W}TR2_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 11/43] arm64: sysreg: Add system instructions trapped by HFGIRT2_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 12/43] arm64: Remove duplicated sysreg encodings Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 13/43] arm64: tools: Resync sysreg.h Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 14/43] arm64: Add syndrome information for trapped LD64B/ST64B{,V,V0} Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 15/43] arm64: Add FEAT_FGT2 capability Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 16/43] KVM: arm64: Tighten handling of unknown FGT groups Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 17/43] KVM: arm64: Simplify handling of negative FGT bits Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 18/43] KVM: arm64: Handle trapping of FEAT_LS64* instructions Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 19/43] KVM: arm64: Restrict ACCDATA_EL1 undef to FEAT_LS64_ACCDATA being disabled Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 20/43] KVM: arm64: Don't treat HCRX_EL2 as a FGT register Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 21/43] KVM: arm64: Plug FEAT_GCS handling Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 22/43] KVM: arm64: Compute FGT masks from KVM's own FGT tables Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 23/43] KVM: arm64: Add description of FGT bits leading to EC!=0x18 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 24/43] KVM: arm64: Use computed masks as sanitisers for FGT registers Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 25/43] KVM: arm64: Unconditionally configure fine-grain traps Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 26/43] KVM: arm64: Propagate FGT masks to the nVHE hypervisor Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 27/43] KVM: arm64: Use computed FGT masks to setup FGT registers Marc Zyngier
2025-05-08 13:49 ` Joey Gouly
2025-05-06 16:43 ` [PATCH v4 28/43] KVM: arm64: Remove hand-crafted masks for " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 29/43] KVM: arm64: Use KVM-specific HCRX_EL2 RES0 mask Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 30/43] KVM: arm64: Handle PSB CSYNC traps Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 31/43] KVM: arm64: Switch to table-driven FGU configuration Marc Zyngier
2025-05-08 15:58 ` Joey Gouly
2025-05-10 9:56 ` Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 32/43] KVM: arm64: Validate FGT register descriptions against RES0 masks Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 33/43] KVM: arm64: Use FGT feature maps to drive RES0 bits Marc Zyngier
2025-05-15 15:24 ` Joey Gouly
2025-05-06 16:43 ` [PATCH v4 34/43] KVM: arm64: Allow kvm_has_feat() to take variable arguments Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 35/43] KVM: arm64: Use HCRX_EL2 feature map to drive fixed-value bits Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 36/43] KVM: arm64: Use HCR_EL2 " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 37/43] KVM: arm64: Add FEAT_FGT2 registers to the VNCR page Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 38/43] KVM: arm64: Add sanitisation for FEAT_FGT2 registers Marc Zyngier
2025-05-15 16:04 ` Joey Gouly
2025-05-06 16:43 ` [PATCH v4 39/43] KVM: arm64: Add trap routing " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 40/43] KVM: arm64: Add context-switch " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 41/43] KVM: arm64: Allow sysreg ranges for FGT descriptors Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 42/43] KVM: arm64: Add FGT descriptors for FEAT_FGT2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 43/43] KVM: arm64: Handle TSB CSYNC traps Marc Zyngier
2025-05-19 11:59 ` [PATCH v4 00/43] KVM: arm64: Revamp Fine Grained Trap handling Marc Zyngier
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