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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bg+0e6v6ZFzpaKXGPFx7D1MKdC9fhdRzQ7vBrXA6o+k=; b=xX8VQZ8n5MiRWWP6ss7Zf38oKM7ifFk38/IgAYC3VmZf64YCHNKm/hlpqNniVfhO9X9hsc8REZiPjJlmm2ZZitV9nsNp8N2BcnRZtK9JRgjbMlyUvum8iQfxk69iuTud7Fj7F0oLdWcdGiM6a4jNAWvCfnKc2PEI2lJazvO5q6A= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 02/10] vpci/header: Emulate legacy capability list for dom0 Date: Fri, 9 May 2025 17:05:34 +0800 Message-ID: <20250509090542.2199676-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250509090542.2199676-1-Jiqian.Chen@amd.com> References: <20250509090542.2199676-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2025 09:06:03.8493 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf61a3c4-18af-4595-ebd8-08dd8ed8b9ec X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4480 Current logic of emulating legacy capability list is only for domU. So, expand it to emulate for dom0 too. Then it will be easy to hide a capability whose initialization fails in a function. And restrict adding PCI_STATUS register only for domU since dom0 has no limitation to access that register. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" --- v3->v4 changes: * Also pass supported_caps to pci_find_next_cap_ttl() for dom0 since the n is zero when dom0, and add a comment to explain it. * Restrict adding PCI_STATUS register only for domU since dom0 has no limitation to access that register. * For dom0 register handler, set vpci_hw_write8 to it instead of NULL. v2->v3 changes: * Not to add handler of PCI_CAP_LIST_ID when domain is dom0. v1->v2 changes: new patch. Best regards, Jiqian Chen. --- xen/drivers/vpci/header.c | 53 ++++++++++++++++++++++++--------------- xen/drivers/vpci/vpci.c | 6 +++++ xen/include/xen/vpci.h | 2 ++ 3 files changed, 41 insertions(+), 20 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 3e9b44454b43..a06c518c506c 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -749,9 +749,9 @@ static int vpci_init_capability_list(struct pci_dev *pdev) { int rc; bool mask_cap_list = false; + bool is_hwdom = is_hardware_domain(pdev->domain); - if ( !is_hardware_domain(pdev->domain) && - pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST ) + if ( pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST ) { /* Only expose capabilities to the guest that vPCI can handle. */ unsigned int next, ttl = 48; @@ -759,12 +759,18 @@ static int vpci_init_capability_list(struct pci_dev *pdev) PCI_CAP_ID_MSI, PCI_CAP_ID_MSIX, }; + /* + * For dom0, we should expose all capabilities instead of a fixed + * capabilities array, so setting n to 0 here is to get the next + * capability position directly in pci_find_next_cap_ttl. + */ + const unsigned int n = is_hwdom ? 0 : ARRAY_SIZE(supported_caps); next = pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, - supported_caps, - ARRAY_SIZE(supported_caps), &ttl); + supported_caps, n, &ttl); - rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + rc = vpci_add_register(pdev->vpci, vpci_read_val, + is_hwdom ? vpci_hw_write8 : NULL, PCI_CAPABILITY_LIST, 1, (void *)(uintptr_t)next); if ( rc ) @@ -772,7 +778,7 @@ static int vpci_init_capability_list(struct pci_dev *pdev) next &= ~3; - if ( !next ) + if ( !next && !is_hwdom ) /* * If we don't have any supported capabilities to expose to the * guest, mask the PCI_STATUS_CAP_LIST bit in the status @@ -786,15 +792,18 @@ static int vpci_init_capability_list(struct pci_dev *pdev) next = pci_find_next_cap_ttl(pdev->sbdf, pos + PCI_CAP_LIST_NEXT, - supported_caps, - ARRAY_SIZE(supported_caps), &ttl); + supported_caps, n, &ttl); - rc = vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, - pos + PCI_CAP_LIST_ID, 1, NULL); - if ( rc ) - return rc; + if ( !is_hwdom ) + { + rc = vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + } - rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + rc = vpci_add_register(pdev->vpci, vpci_read_val, + is_hwdom ? vpci_hw_write8 : NULL, pos + PCI_CAP_LIST_NEXT, 1, (void *)(uintptr_t)next); if ( rc ) @@ -805,13 +814,17 @@ static int vpci_init_capability_list(struct pci_dev *pdev) } /* Utilize rsvdp_mask to hide PCI_STATUS_CAP_LIST from the guest. */ - return vpci_add_register_mask(pdev->vpci, vpci_hw_read16, vpci_hw_write16, - PCI_STATUS, 2, NULL, - PCI_STATUS_RO_MASK & - ~(mask_cap_list ? PCI_STATUS_CAP_LIST : 0), - PCI_STATUS_RW1C_MASK, - mask_cap_list ? PCI_STATUS_CAP_LIST : 0, - PCI_STATUS_RSVDZ_MASK); + return is_hwdom ? 0 : vpci_add_register_mask(pdev->vpci, vpci_hw_read16, + vpci_hw_write16, PCI_STATUS, + 2, NULL, + PCI_STATUS_RO_MASK & + ~(mask_cap_list ? + PCI_STATUS_CAP_LIST : + 0), + PCI_STATUS_RW1C_MASK, + mask_cap_list ? + PCI_STATUS_CAP_LIST : 0, + PCI_STATUS_RSVDZ_MASK); } static int cf_check init_header(struct pci_dev *pdev) diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 1e6aa5d799b9..cf3326a966d0 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -226,6 +226,12 @@ uint32_t cf_check vpci_hw_read32( return pci_conf_read32(pdev->sbdf, reg); } +void cf_check vpci_hw_write8( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write8(pdev->sbdf, reg, val); +} + void cf_check vpci_hw_write16( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 475981cb8155..fc8d5b470b0b 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -76,6 +76,8 @@ uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( const struct pci_dev *pdev, unsigned int reg, void *data); +void cf_check vpci_hw_write8( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data); void cf_check vpci_hw_write16( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data); -- 2.34.1