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From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, ville.syrjala@intel.com
Subject: [PATCH v5 05/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff
Date: Tue, 13 May 2025 10:46:48 +0530	[thread overview]
Message-ID: <20250513051700.507389-6-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20250513051700.507389-1-mitulkumar.ajitkumar.golani@intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

--v2:
- Correct Author details.

--v3:
- Separate register details from this  patch.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 57 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  5 +++
 2 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index adfd231eb578..ab4f8def821c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -746,3 +746,60 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display,
+			    TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display,
+			    TRANS_VRR_DCB_ADJ_VMAX_CFG(display, cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display,
+			    TRANS_VRR_FLIPLINE_DCB(display, cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(display, cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..e62b8b50aec6 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1


  parent reply	other threads:[~2025-05-13  5:19 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-13  5:16 [PATCH v5 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-05-13  5:16 ` [PATCH v5 01/17] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
2025-05-13  5:16 ` [PATCH v5 02/17] drm/i915/display: Add source param for dc balance Mitul Golani
2025-05-13  5:16 ` [PATCH v5 03/17] drm/i915/display: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-05-30  6:22   ` Nautiyal, Ankit K
2025-05-13  5:16 ` [PATCH v5 04/17] drm/i915/display: Add VRR DC balance registers Mitul Golani
2025-05-13  7:15   ` Jani Nikula
2025-05-13  5:16 ` Mitul Golani [this message]
2025-05-13  5:16 ` [PATCH v5 06/17] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-05-13  5:16 ` [PATCH v5 07/17] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-05-13  5:16 ` [PATCH v5 08/17] drm/i915/vrr: Add compute config " Mitul Golani
2025-05-13  5:16 ` [PATCH v5 09/17] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-05-27  6:17   ` Nautiyal, Ankit K
2025-05-13  5:16 ` [PATCH v5 10/17] drm/i915: Extract vrr_vblank_start() Mitul Golani
2025-05-13  5:16 ` [PATCH v5 11/17] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-05-13  5:16 ` [PATCH v5 12/17] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-05-13  5:16 ` [PATCH v5 13/17] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
2025-05-13  5:16 ` [PATCH v5 14/17] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-05-13  5:16 ` [PATCH v5 15/17] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-05-13  5:16 ` [PATCH v5 16/17] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL Mitul Golani
2025-05-13  5:17 ` [PATCH v5 17/17] drm/i915/vrr: Enable DC Balance bit Mitul Golani
2025-05-13  5:24 ` ✓ CI.Patch_applied: success for Enable/Disable DC balance along with VRR DSB (rev5) Patchwork
2025-05-13  5:25 ` ✗ CI.checkpatch: warning " Patchwork
2025-05-13  5:26 ` ✓ CI.KUnit: success " Patchwork
2025-05-13  5:36 ` ✗ CI.Build: failure " Patchwork
2025-05-13  6:02 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2025-05-13  6:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-05-13  6:26 ` ✗ i915.CI.BAT: failure " Patchwork
2025-05-15  7:55   ` Golani, Mitulkumar Ajitkumar
2025-05-13 15:51 ` ✓ CI.Patch_applied: success " Patchwork
2025-05-13 15:51 ` ✗ CI.checkpatch: warning " Patchwork
2025-05-13 15:52 ` ✓ CI.KUnit: success " Patchwork
2025-05-13 16:10 ` ✓ CI.Build: " Patchwork
2025-05-14 17:24 ` ✓ CI.Patch_applied: success for Enable/Disable DC balance along with VRR DSB (rev6) Patchwork
2025-05-14 17:24 ` ✗ CI.checkpatch: warning " Patchwork
2025-05-14 17:25 ` ✓ CI.KUnit: success " Patchwork
2025-05-14 17:36 ` ✓ CI.Build: " Patchwork
2025-05-14 17:38 ` ✓ CI.Hooks: " Patchwork
2025-05-14 17:40 ` ✗ CI.checksparse: warning " Patchwork
2025-05-14 18:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-05-15  1:36 ` ✓ Xe.CI.Full: " Patchwork
2025-05-15  8:20 ` ✓ i915.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev5) Patchwork
2025-05-15  9:56 ` ✗ i915.CI.Full: failure " Patchwork
2025-05-27  0:39 ` ✗ CI.Patch_applied: failure for Enable/Disable DC balance along with VRR DSB (rev6) Patchwork

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