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[209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6f6e39e7272si151769816d6.98.2025.05.15.01.16.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 15 May 2025 01:16:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uFTiY-0005tQ-Bh; Thu, 15 May 2025 04:13:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFTi1-0003Im-68; Thu, 15 May 2025 04:12:54 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uFThz-0001HG-9B; Thu, 15 May 2025 04:12:52 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 15 May 2025 16:10:17 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 15 May 2025 16:10:17 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v3 27/28] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Date: Thu, 15 May 2025 16:09:59 +0800 Message-ID: <20250515081008.583578-28-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515081008.583578-1-jamin_lin@aspeedtech.com> References: <20250515081008.583578-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: ZvDehesEqedp Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and "HACE_HASH_KEY_BUFF_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/aspeed-hace-utils.h | 2 ++ tests/qtest/aspeed-hace-utils.c | 14 ++++++++++++++ tests/qtest/aspeed_hace-test.c | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-utils.h index de8055a1db..c8b2ec45af 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -50,9 +50,11 @@ struct AspeedSgList { struct AspeedMasks { uint32_t src; uint32_t dest; + uint32_t key; uint32_t len; uint32_t src_hi; uint32_t dest_hi; + uint32_t key_hi; }; void aspeed_test_md5(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-utils.c index cb78f18117..0f7f911e5e 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -591,6 +591,8 @@ void aspeed_test_addresses(const char *machine, const uint32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); /* Check that the address masking is correct */ @@ -609,6 +611,14 @@ void aspeed_test_addresses(const char *machine, const uint32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, expected->dest_hi); + qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, + expected->key); + + qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, + expected->key_hi); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, expected->len); @@ -618,6 +628,8 @@ void aspeed_test_addresses(const char *machine, const uint32_t base, qtest_writel(s, base + HACE_HASH_SRC_HI, 0); qtest_writel(s, base + HACE_HASH_DIGEST, 0); qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); + qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0); + qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0); qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); /* Check that all bits are now zero */ @@ -625,6 +637,8 @@ void aspeed_test_addresses(const char *machine, const uint32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); qtest_quit(s); diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index 31890d574e..38777020ca 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -13,24 +13,28 @@ static const struct AspeedMasks ast1030_masks = { .src = 0x7fffffff, .dest = 0x7ffffff8, + .key = 0x7ffffff8, .len = 0x0fffffff, }; static const struct AspeedMasks ast2600_masks = { .src = 0x7fffffff, .dest = 0x7ffffff8, + .key = 0x7ffffff8, .len = 0x0fffffff, }; static const struct AspeedMasks ast2500_masks = { .src = 0x3fffffff, .dest = 0x3ffffff8, + .key = 0x3fffffc0, .len = 0x0fffffff, }; static const struct AspeedMasks ast2400_masks = { .src = 0x0fffffff, .dest = 0x0ffffff8, + .key = 0x0fffffc0, .len = 0x0fffffff, }; -- 2.43.0