From: Tomasz Lis <tomasz.lis@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: "Michał Winiarski" <michal.winiarski@intel.com>,
"Michał Wajdeczko" <michal.wajdeczko@intel.com>,
"Piotr Piórkowski" <piotr.piorkowski@intel.com>,
"Matthew Brost" <matthew.brost@intel.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>
Subject: [PATCH v2 6/7] drm/xe/vf: Rebase MEMIRQ structures for all contexts after migration
Date: Fri, 16 May 2025 00:18:26 +0200 [thread overview]
Message-ID: <20250515221827.1493032-7-tomasz.lis@intel.com> (raw)
In-Reply-To: <20250515221827.1493032-1-tomasz.lis@intel.com>
All contexts require an update of state data, as the data includes
GGTT references to memirq-related buffers.
Default contexts need these references updated as well, because they
are not refreshed when a new context is created from them.
v2: Update addresses by xe_lrc_write_ctx_reg() rather than
set_memory_based_intr()
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 4 +++-
drivers/gpu/drm/xe/xe_lrc.c | 35 ++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_lrc.h | 2 ++
drivers/gpu/drm/xe/xe_sriov_vf.c | 13 ++++++++++-
4 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index d03600519b27..9814e29a09e1 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -1046,6 +1046,8 @@ void xe_exec_queue_contexts_hwsp_rebase(struct xe_exec_queue *eq)
{
int i;
- for (i = 0; i < eq->width; ++i)
+ for (i = 0; i < eq->width; ++i) {
+ xe_lrc_update_memirq_regs_with_address(eq->hwe, eq->lrc[i]);
xe_lrc_update_hwctx_regs_with_address(eq->lrc[i]);
+ }
}
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 525565480aef..dc748f6df8ff 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -898,6 +898,41 @@ static void *empty_lrc_data(struct xe_hw_engine *hwe)
return data;
}
+/**
+ * xe_default_lrc_update_memirq_regs_with_address - Re-compute GGTT references in default LRC
+ * of given engine.
+ * @hwe: the &xe_hw_engine struct instance
+ */
+void xe_default_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe)
+{
+ struct xe_gt *gt = hwe->gt;
+ u32 *regs;
+
+ if (!gt->default_lrc[hwe->class])
+ return;
+
+ regs = gt->default_lrc[hwe->class] + LRC_PPHWSP_SIZE;
+ set_memory_based_intr(regs, hwe);
+}
+
+/**
+ * xe_lrc_update_memirq_regs_with_address - Re-compute GGTT references in mem interrupt data
+ * for given LRC.
+ * @hwe: the &xe_hw_engine struct instance
+ * @lrc: the &xe_lrc struct instance
+ */
+void xe_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe, struct xe_lrc *lrc)
+{
+ struct xe_memirq *memirq = >_to_tile(hwe->gt)->memirq;
+
+ xe_lrc_write_ctx_reg(lrc, CTX_INT_MASK_ENABLE_PTR,
+ xe_memirq_enable_ptr(memirq));
+ xe_lrc_write_ctx_reg(lrc, CTX_INT_STATUS_REPORT_PTR,
+ xe_memirq_status_ptr(memirq, hwe));
+ xe_lrc_write_ctx_reg(lrc, CTX_INT_SRC_REPORT_PTR,
+ xe_memirq_source_ptr(memirq, hwe));
+}
+
static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm)
{
u64 desc = xe_vm_pdp4_descriptor(vm, gt_to_tile(lrc->gt));
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index e7a99cfd0abe..3f0ae3affafe 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -89,6 +89,8 @@ u32 xe_lrc_indirect_ring_ggtt_addr(struct xe_lrc *lrc);
u32 xe_lrc_ggtt_addr(struct xe_lrc *lrc);
u32 *xe_lrc_regs(struct xe_lrc *lrc);
void xe_lrc_update_hwctx_regs_with_address(struct xe_lrc *lrc);
+void xe_default_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe);
+void xe_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe, struct xe_lrc *lrc);
u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr);
void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val);
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf.c b/drivers/gpu/drm/xe/xe_sriov_vf.c
index 0e73b79b3a73..3ac042da4b87 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf.c
@@ -225,13 +225,24 @@ static int vf_post_migration_requery_guc(struct xe_device *xe)
return ret;
}
+static void xe_gt_default_lrcs_hwsp_rebase(struct xe_gt *gt)
+{
+ struct xe_hw_engine *hwe;
+ enum xe_hw_engine_id id;
+
+ for_each_hw_engine(hwe, gt, id)
+ xe_default_lrc_update_memirq_regs_with_address(hwe);
+}
+
static void vf_post_migration_fixup_contexts(struct xe_device *xe)
{
struct xe_gt *gt;
unsigned int id;
- for_each_gt(gt, xe, id)
+ for_each_gt(gt, xe, id) {
+ xe_gt_default_lrcs_hwsp_rebase(gt);
xe_guc_contexts_hwsp_rebase(>->uc.guc);
+ }
}
static void vf_post_migration_fixup_ctb(struct xe_device *xe)
--
2.25.1
next prev parent reply other threads:[~2025-05-15 22:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 22:18 [PATCH v2 0/7] drm/xe/vf: Post-migration recovery of queues and jobs Tomasz Lis
2025-05-15 22:18 ` [PATCH v2 1/7] drm/xe/sa: Avoid caching GGTT address within the manager Tomasz Lis
2025-05-15 22:18 ` [PATCH v2 2/7] drm/xe/vf: Finish RESFIX by reset if CTB not enabled Tomasz Lis
2025-05-15 22:18 ` [PATCH v2 3/7] drm/xe/vf: Pause submissions during RESFIX fixups Tomasz Lis
2025-05-16 17:30 ` Michal Wajdeczko
2025-05-19 23:07 ` Lis, Tomasz
2025-05-15 22:18 ` [PATCH v2 4/7] drm/xe: Block reset while recovering from VF migration Tomasz Lis
2025-05-15 22:18 ` [PATCH v2 5/7] drm/xe/vf: Rebase HWSP of all contexts after migration Tomasz Lis
2025-05-16 17:01 ` Michal Wajdeczko
2025-05-15 22:18 ` Tomasz Lis [this message]
2025-05-16 17:15 ` [PATCH v2 6/7] drm/xe/vf: Rebase MEMIRQ structures for " Michal Wajdeczko
2025-05-15 22:18 ` [PATCH v2 7/7] drm/xe/vf: Post migration, repopulate ring area for pending request Tomasz Lis
2025-05-15 22:24 ` ✓ CI.Patch_applied: success for drm/xe/vf: Post-migration recovery of queues and jobs (rev2) Patchwork
2025-05-15 22:25 ` ✗ CI.checkpatch: warning " Patchwork
2025-05-15 22:26 ` ✓ CI.KUnit: success " Patchwork
2025-05-15 22:36 ` ✓ CI.Build: " Patchwork
2025-05-15 22:39 ` ✓ CI.Hooks: " Patchwork
2025-05-15 22:40 ` ✓ CI.checksparse: " Patchwork
2025-05-15 23:03 ` ✓ Xe.CI.BAT: " Patchwork
2025-05-16 14:21 ` ✓ Xe.CI.Full: " Patchwork
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