From: Sairaj Kodilkar <sarunkod@amd.com>
To: <qemu-devel@nongnu.org>
Cc: <mst@redhat.com>, <marcel.apfelbaum@gmail.com>,
<pbonzini@redhat.com>, <richard.henderson@linaro.org>,
<eduardo@habkost.net>, <suravee.suthikulpanit@amd.com>,
<alejandro.j.jimenez@oracle.com>, <joao.m.martins@oracle.com>,
<sarunkod@amd.com>, Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH v3 1/2] hw/i386/amd_iommu: Fix device setup failure when PT is on.
Date: Fri, 16 May 2025 15:35:34 +0530 [thread overview]
Message-ID: <20250516100535.4980-2-sarunkod@amd.com> (raw)
In-Reply-To: <20250516100535.4980-1-sarunkod@amd.com>
Commit c1f46999ef506 ("amd_iommu: Add support for pass though mode")
introduces the support for "pt" flag by enabling nodma memory when
"pt=off". This allowed VFIO devices to successfully register notifiers
by using nodma region.
But, This also broke things when guest is booted with the iommu=nopt
because, devices bypass the IOMMU and use untranslated addresses (IOVA) to
perform DMA reads/writes to the nodma memory region, ultimately resulting in
a failure to setup the devices in the guest.
Fix the above issue by always enabling the amdvi_dev_as->iommu memory region.
But this will once again cause VFIO devices to fail while registering the
notifiers with AMD IOMMU memory region.
Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode")
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
---
hw/i386/amd_iommu.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 5f9b95279997..df8ba5d39ada 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -1426,7 +1426,6 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
AMDVIState *s = opaque;
AMDVIAddressSpace **iommu_as, *amdvi_dev_as;
int bus_num = pci_bus_num(bus);
- X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
iommu_as = s->address_spaces[bus_num];
@@ -1486,15 +1485,8 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
AMDVI_INT_ADDR_FIRST,
&amdvi_dev_as->iommu_ir, 1);
- if (!x86_iommu->pt_supported) {
- memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false);
- memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu),
- true);
- } else {
- memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu),
- false);
- memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, true);
- }
+ memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false);
+ memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), true);
}
return &iommu_as[devfn]->as;
}
--
2.34.1
next prev parent reply other threads:[~2025-05-16 10:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-16 10:05 [PATCH v3 0/2] amd_iommu: Fixes Sairaj Kodilkar
2025-05-16 10:05 ` Sairaj Kodilkar [this message]
2025-05-16 14:43 ` [PATCH v3 1/2] hw/i386/amd_iommu: Fix device setup failure when PT is on Philippe Mathieu-Daudé
2025-05-19 3:59 ` Sairaj Kodilkar
2025-05-16 10:05 ` [PATCH v3 2/2] hw/i386/amd_iommu: Fix xtsup when vcpus < 255 Sairaj Kodilkar
2025-05-16 14:38 ` Philippe Mathieu-Daudé
2025-05-19 7:35 ` Vasant Hegde
2025-05-16 10:36 ` [PATCH v3 0/2] amd_iommu: Fixes Michael S. Tsirkin
2025-05-16 10:45 ` Sairaj Kodilkar
2025-06-02 20:54 ` Michael Tokarev
2025-06-10 8:33 ` Sairaj Kodilkar
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