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Mon, 19 May 2025 09:35:47 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::ce80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a35ca8d258sm13298494f8f.100.2025.05.19.09.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 09:35:47 -0700 (PDT) Date: Mon, 19 May 2025 18:35:46 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: Alexandre Ghiti , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH RFC] target: riscv: Fix satp mode initialization based on profile Message-ID: <20250519-a153c03e434d1bf31498eb01@orel> References: <20250516122319.4100121-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Mon, May 19, 2025 at 09:48:14AM -0300, Daniel Henrique Barboza wrote: > > > On 5/16/25 9:23 AM, Alexandre Ghiti wrote: > > The satp mode is set using the svXX properties, but that actually > > restricts the satp mode to the minimum required by the profile and > > prevents the use of higher satp modes. > > For rva23s64, in "Optional Extensions" we'll find: The keyword is "Optional". The profile should only set sv39 since that's what rva23 (and rv22) have for the mandatory support. sv48 and sv57 are both optional so, while the user should be allowed to turn them on, just like other optional extensions, they shouldn't be on by default since we don't set any optional extensions on by default. So we don't want this change, but fixing any bugs with the first hart vs. the other harts is of course necessary. Thanks, drew > > https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc > > - Sv48 Page-based 48-bit virtual-memory system. > - Sv57 Page-based 57-bit virtual-memory system. > > So in theory we could go up to sv57 for rva23s64 (and rva22s64, just checked). > Changing satp_mode to the maximum allowed seems sensible. > > But allowing all satp modes to go in a profile defeats the purpose, doesn't it? > None of the existing profiles in QEMU claims supports sv64. Granted, I'm not a > satp expert, but removing the satp restriction in profiles doesn't seem right. > > > Thanks, > > Daniel > > > > > > Fix this by not setting any svXX property and allow all satp mode to be > > supported. > > > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/tcg/tcg-cpu.c | 3 --- > > 1 file changed, 3 deletions(-) > > > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > > index 5aef9eef36..ca2d2950eb 100644 > > --- a/target/riscv/tcg/tcg-cpu.c > > +++ b/target/riscv/tcg/tcg-cpu.c > > @@ -1232,9 +1232,6 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, > > #ifndef CONFIG_USER_ONLY > > if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { > > object_property_set_bool(obj, "mmu", true, NULL); > > - const char *satp_prop = satp_mode_str(profile->satp_mode, > > - riscv_cpu_is_32bit(cpu)); > > - object_property_set_bool(obj, satp_prop, profile->enabled, NULL); > > } > > #endif > >