From: Ard Biesheuvel <ardb+git@google.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Ingo Molnar <mingo@kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Brian Gerst <brgerst@gmail.com>,
"Kirill A. Shutemov" <kirill@shutemov.name>,
Borislav Petkov <bp@alien8.de>
Subject: [PATCH v5 6/7] x86/boot: Drop 5-level paging related global variable
Date: Tue, 20 May 2025 12:41:45 +0200 [thread overview]
Message-ID: <20250520104138.2734372-15-ardb+git@google.com> (raw)
In-Reply-To: <20250520104138.2734372-9-ardb+git@google.com>
From: Ard Biesheuvel <ardb@kernel.org>
The variable __pgtable_l5_enabled is no longer used so it can be
dropped.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/x86/boot/compressed/misc.h | 1 -
arch/x86/boot/compressed/pgtable_64.c | 6 ------
arch/x86/boot/startup/map_kernel.c | 16 +---------------
arch/x86/include/asm/pgtable_64_types.h | 2 --
arch/x86/kernel/head64.c | 2 --
5 files changed, 1 insertion(+), 26 deletions(-)
diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h
index 7f79c426f542..d6860b50afaf 100644
--- a/arch/x86/boot/compressed/misc.h
+++ b/arch/x86/boot/compressed/misc.h
@@ -190,7 +190,6 @@ static inline int count_immovable_mem_regions(void) { return 0; }
#endif
/* ident_map_64.c */
-extern unsigned int __pgtable_l5_enabled;
extern void kernel_add_identity_map(unsigned long start, unsigned long end);
/* Used by PAGE_KERN* macros: */
diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index 965fca150e68..4772919411a9 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -10,9 +10,6 @@
#define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */
#define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */
-/* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */
-unsigned int __section(".data") __pgtable_l5_enabled;
-
/* Buffer to preserve trampoline memory */
static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
@@ -118,9 +115,6 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable)
if (!cmdline_find_option_bool("no5lvl") &&
native_cpuid_eax(0) >= 7 && (native_cpuid_ecx(7) & BIT(16))) {
l5_required = true;
-
- /* Initialize variables for 5-level paging */
- __pgtable_l5_enabled = 1;
}
/*
diff --git a/arch/x86/boot/startup/map_kernel.c b/arch/x86/boot/startup/map_kernel.c
index 5d3c6108f1c3..328a343bc355 100644
--- a/arch/x86/boot/startup/map_kernel.c
+++ b/arch/x86/boot/startup/map_kernel.c
@@ -14,20 +14,6 @@
extern pmd_t early_dynamic_pgts[EARLY_DYNAMIC_PAGE_TABLES][PTRS_PER_PMD];
extern unsigned int next_early_pgt;
-static inline bool check_la57_support(void)
-{
- /*
- * 5-level paging is detected and enabled at kernel decompression
- * stage. Only check if it has been enabled there.
- */
- if (!(native_read_cr4() & X86_CR4_LA57))
- return false;
-
- __pgtable_l5_enabled = 1;
-
- return true;
-}
-
static unsigned long __head sme_postprocess_startup(struct boot_params *bp,
pmdval_t *pmd,
unsigned long p2v_offset)
@@ -97,7 +83,7 @@ unsigned long __head __startup_64(unsigned long p2v_offset,
bool la57;
int i;
- la57 = check_la57_support();
+ la57 = pgtable_l5_enabled();
/* Is the address too large? */
if (physaddr >> MAX_PHYSMEM_BITS)
diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
index ed847a90cf4f..3c56b98b87b0 100644
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -22,8 +22,6 @@ typedef unsigned long pgprotval_t;
typedef struct { pteval_t pte; } pte_t;
typedef struct { pmdval_t pmd; } pmd_t;
-extern unsigned int __pgtable_l5_enabled;
-
#ifndef pgdir_shift
DECLARE_PER_CPU_CACHE_HOT(u8, __pgdir_shift);
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 5e5da6574a83..137c93498601 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -48,8 +48,6 @@ unsigned int __initdata next_early_pgt;
SYM_PIC_ALIAS(next_early_pgt);
pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
-unsigned int __pgtable_l5_enabled __ro_after_init;
-
unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
EXPORT_SYMBOL(page_offset_base);
unsigned long vmalloc_base __ro_after_init = __VMALLOC_BASE_L4;
--
2.49.0.1101.gccaa498523-goog
next prev parent reply other threads:[~2025-05-20 10:42 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 10:41 [PATCH v5 0/7] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 1/7] x86/mm: Decouple MAX_PHYSMEM_BITS from LA57 state Ard Biesheuvel
2025-05-20 10:59 ` Kirill A. Shutemov
2025-05-20 11:27 ` Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 2/7] x86/mm: Use a single cache hot per-CPU variable to record pgdir_shift Ard Biesheuvel
2025-05-20 11:03 ` Kirill A. Shutemov
2025-05-20 11:28 ` Ard Biesheuvel
2025-05-20 14:35 ` Borislav Petkov
2025-05-20 17:03 ` Ard Biesheuvel
2025-05-20 17:38 ` Borislav Petkov
2025-05-20 17:46 ` Ard Biesheuvel
2025-05-20 18:01 ` Borislav Petkov
2025-05-20 18:28 ` Linus Torvalds
2025-05-20 18:35 ` Borislav Petkov
2025-05-20 19:49 ` Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 3/7] x86/mm: Define PTRS_PER_P4D in terms of pgdir_shift() Ard Biesheuvel
2025-05-20 11:08 ` Kirill A. Shutemov
2025-05-20 11:29 ` Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 4/7] x86/mm: Derive pgtable_l5_enabled() from pgdir_shift() Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 5/7] x86/boot: Drop USE_EARLY_PGTABLE_L5 definitions Ard Biesheuvel
2025-05-20 10:41 ` Ard Biesheuvel [this message]
2025-05-20 10:41 ` [PATCH v5 7/7] x86/boot: Remove KASAN workaround for 4/5 level paging switch Ard Biesheuvel
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