From: Sasha Levin <sashal@kernel.org>
To: stable@vger.kernel.org
Cc: Eric Naim <dnaim@cachyos.org>, Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH 2/2] drm/amdgpu: read back register after written for VCN v4.0.5
Date: Thu, 22 May 2025 03:38:04 -0400 [thread overview]
Message-ID: <20250521233459-363ebb04fd975b3a@stable.kernel.org> (raw)
In-Reply-To: <20250521165421.293820-2-dnaim@cachyos.org>
[ Sasha's backport helper bot ]
Hi,
✅ All tests passed successfully. No issues detected.
No action required from the submitter.
The upstream commit SHA1 provided is correct: ee7360fc27d6045510f8fe459b5649b2af27811a
WARNING: Author mismatch between patch and upstream commit:
Backport author: Eric Naim<dnaim@cachyos.org>
Commit author: David (Ming Qiang) Wu<David.Wu3@amd.com>
Note: The patch differs from the upstream commit:
---
1: ee7360fc27d60 ! 1: d66acea470dc1 drm/amdgpu: read back register after written for VCN v4.0.5
@@ Metadata
## Commit message ##
drm/amdgpu: read back register after written for VCN v4.0.5
+ commit ee7360fc27d6045510f8fe459b5649b2af27811a upstream
+
On VCN v4.0.5 there is a race condition where the WPTR is not
updated after starting from idle when doorbell is used. Adding
register read-back after written at function end is to ensure
@@ Commit message
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 07c9db090b86e5211188e1b351303fbc673378cf)
Cc: stable@vger.kernel.org
+ Tested-by: Eric Naim <dnaim@cachyos.org>
+ Signed-off-by: Eric Naim <dnaim@cachyos.org>
## drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c ##
-@@ drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c: static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
+@@ drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c: static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
VCN_RB1_DB_CTRL__EN_MASK);
@@ drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c: static int vcn_v4_0_5_start_dpg_mode(st
return 0;
}
-@@ drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c: static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)
+@@ drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c: static int vcn_v4_0_5_start(struct amdgpu_device *adev, int i)
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
---
Results of testing on various branches:
| Branch | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-5.4.y | Success | Success |
next prev parent reply other threads:[~2025-05-22 7:38 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-21 16:54 [PATCH 1/2] drm/amdgpu/vcn4.0.5: split code along instances Eric Naim
2025-05-21 16:54 ` [PATCH 2/2] drm/amdgpu: read back register after written for VCN v4.0.5 Eric Naim
2025-05-22 7:38 ` Sasha Levin [this message]
2025-05-22 7:38 ` [PATCH 1/2] drm/amdgpu/vcn4.0.5: split code along instances Sasha Levin
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