All of lore.kernel.org
 help / color / mirror / Atom feed
From: Anup Patel <apatel@ventanamicro.com>
To: "Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Jassi Brar" <jassisinghbrar@gmail.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Uwe Kleine-König" <ukleinek@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>,
	Rahul Pathak <rpathak@ventanamicro.com>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Atish Patra <atish.patra@linux.dev>,
	Andrew Jones <ajones@ventanamicro.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Anup Patel <anup@brainfault.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v4 04/23] RISC-V: Add defines for the SBI message proxy extension
Date: Sun, 25 May 2025 14:16:51 +0530	[thread overview]
Message-ID: <20250525084710.1665648-5-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com>

Add defines for the new SBI message proxy extension which is part
of the SBI v3.0 specification.

Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/sbi.h | 60 ++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 4dd6aafb8468..d295c26a7c26 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -35,6 +35,7 @@ enum sbi_ext_id {
 	SBI_EXT_DBCN = 0x4442434E,
 	SBI_EXT_STA = 0x535441,
 	SBI_EXT_NACL = 0x4E41434C,
+	SBI_EXT_MPXY = 0x4D505859,
 
 	/* Experimentals extensions must lie within this range */
 	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -402,6 +403,65 @@ enum sbi_ext_nacl_feature {
 #define SBI_NACL_SHMEM_SRET_X(__i)		((__riscv_xlen / 8) * (__i))
 #define SBI_NACL_SHMEM_SRET_X_LAST		31
 
+enum sbi_ext_mpxy_fid {
+	SBI_EXT_MPXY_GET_SHMEM_SIZE,
+	SBI_EXT_MPXY_SET_SHMEM,
+	SBI_EXT_MPXY_GET_CHANNEL_IDS,
+	SBI_EXT_MPXY_READ_ATTRS,
+	SBI_EXT_MPXY_WRITE_ATTRS,
+	SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
+	SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
+	SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS,
+};
+
+enum sbi_mpxy_attribute_id {
+	/* Standard channel attributes managed by MPXY framework */
+	SBI_MPXY_ATTR_MSG_PROT_ID		= 0x00000000,
+	SBI_MPXY_ATTR_MSG_PROT_VER		= 0x00000001,
+	SBI_MPXY_ATTR_MSG_MAX_LEN		= 0x00000002,
+	SBI_MPXY_ATTR_MSG_SEND_TIMEOUT		= 0x00000003,
+	SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT	= 0x00000004,
+	SBI_MPXY_ATTR_CHANNEL_CAPABILITY	= 0x00000005,
+	SBI_MPXY_ATTR_SSE_EVENT_ID		= 0x00000006,
+	SBI_MPXY_ATTR_MSI_CONTROL		= 0x00000007,
+	SBI_MPXY_ATTR_MSI_ADDR_LO		= 0x00000008,
+	SBI_MPXY_ATTR_MSI_ADDR_HI		= 0x00000009,
+	SBI_MPXY_ATTR_MSI_DATA			= 0x0000000A,
+	SBI_MPXY_ATTR_EVENTS_STATE_CONTROL	= 0x0000000B,
+	SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
+	/*
+	 * Message protocol specific attributes, managed by
+	 * the message protocol specification.
+	 */
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_START	= 0x80000000,
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_END		= 0xffffffff
+};
+
+/* Possible values of MSG_PROT_ID attribute */
+enum sbi_mpxy_msgproto_id {
+	SBI_MPXY_MSGPROTO_RPMI_ID = 0x0,
+};
+
+/** RPMI message protocol specific MPXY attributes */
+enum sbi_mpxy_rpmi_attribute_id {
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
+	SBI_MPXY_RPMI_ATTR_MAX_ID,
+};
+
+/* Encoding of MSG_PROT_VER attribute */
+#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver)	(((__ver) >> 16) & 0xffff)
+#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver)	((__ver) & 0xffff)
+#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min)	(((__maj) << 16) | (__min))
+
+/* Capabilities available through CHANNEL_CAPABILITY attribute */
+#define SBI_MPXY_CHAN_CAP_MSI			BIT(0)
+#define SBI_MPXY_CHAN_CAP_SSE			BIT(1)
+#define SBI_MPXY_CHAN_CAP_EVENTS_STATE		BIT(2)
+#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP	BIT(3)
+#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP	BIT(4)
+#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS	BIT(5)
+
 /* SBI spec version fields */
 #define SBI_SPEC_VERSION_DEFAULT	0x1
 #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
-- 
2.43.0


WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: "Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Jassi Brar" <jassisinghbrar@gmail.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Uwe Kleine-König" <ukleinek@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
	devicetree@vger.kernel.org,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atish.patra@linux.dev>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Anup Patel <anup@brainfault.org>,
	linux-kernel@vger.kernel.org,
	Samuel Holland <samuel.holland@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org, Len Brown <lenb@kernel.org>,
	linux-clk@vger.kernel.org,
	Rahul Pathak <rpathak@ventanamicro.com>
Subject: [PATCH v4 04/23] RISC-V: Add defines for the SBI message proxy extension
Date: Sun, 25 May 2025 14:16:51 +0530	[thread overview]
Message-ID: <20250525084710.1665648-5-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com>

Add defines for the new SBI message proxy extension which is part
of the SBI v3.0 specification.

Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/sbi.h | 60 ++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 4dd6aafb8468..d295c26a7c26 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -35,6 +35,7 @@ enum sbi_ext_id {
 	SBI_EXT_DBCN = 0x4442434E,
 	SBI_EXT_STA = 0x535441,
 	SBI_EXT_NACL = 0x4E41434C,
+	SBI_EXT_MPXY = 0x4D505859,
 
 	/* Experimentals extensions must lie within this range */
 	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -402,6 +403,65 @@ enum sbi_ext_nacl_feature {
 #define SBI_NACL_SHMEM_SRET_X(__i)		((__riscv_xlen / 8) * (__i))
 #define SBI_NACL_SHMEM_SRET_X_LAST		31
 
+enum sbi_ext_mpxy_fid {
+	SBI_EXT_MPXY_GET_SHMEM_SIZE,
+	SBI_EXT_MPXY_SET_SHMEM,
+	SBI_EXT_MPXY_GET_CHANNEL_IDS,
+	SBI_EXT_MPXY_READ_ATTRS,
+	SBI_EXT_MPXY_WRITE_ATTRS,
+	SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
+	SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
+	SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS,
+};
+
+enum sbi_mpxy_attribute_id {
+	/* Standard channel attributes managed by MPXY framework */
+	SBI_MPXY_ATTR_MSG_PROT_ID		= 0x00000000,
+	SBI_MPXY_ATTR_MSG_PROT_VER		= 0x00000001,
+	SBI_MPXY_ATTR_MSG_MAX_LEN		= 0x00000002,
+	SBI_MPXY_ATTR_MSG_SEND_TIMEOUT		= 0x00000003,
+	SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT	= 0x00000004,
+	SBI_MPXY_ATTR_CHANNEL_CAPABILITY	= 0x00000005,
+	SBI_MPXY_ATTR_SSE_EVENT_ID		= 0x00000006,
+	SBI_MPXY_ATTR_MSI_CONTROL		= 0x00000007,
+	SBI_MPXY_ATTR_MSI_ADDR_LO		= 0x00000008,
+	SBI_MPXY_ATTR_MSI_ADDR_HI		= 0x00000009,
+	SBI_MPXY_ATTR_MSI_DATA			= 0x0000000A,
+	SBI_MPXY_ATTR_EVENTS_STATE_CONTROL	= 0x0000000B,
+	SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
+	/*
+	 * Message protocol specific attributes, managed by
+	 * the message protocol specification.
+	 */
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_START	= 0x80000000,
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_END		= 0xffffffff
+};
+
+/* Possible values of MSG_PROT_ID attribute */
+enum sbi_mpxy_msgproto_id {
+	SBI_MPXY_MSGPROTO_RPMI_ID = 0x0,
+};
+
+/** RPMI message protocol specific MPXY attributes */
+enum sbi_mpxy_rpmi_attribute_id {
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
+	SBI_MPXY_RPMI_ATTR_MAX_ID,
+};
+
+/* Encoding of MSG_PROT_VER attribute */
+#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver)	(((__ver) >> 16) & 0xffff)
+#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver)	((__ver) & 0xffff)
+#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min)	(((__maj) << 16) | (__min))
+
+/* Capabilities available through CHANNEL_CAPABILITY attribute */
+#define SBI_MPXY_CHAN_CAP_MSI			BIT(0)
+#define SBI_MPXY_CHAN_CAP_SSE			BIT(1)
+#define SBI_MPXY_CHAN_CAP_EVENTS_STATE		BIT(2)
+#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP	BIT(3)
+#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP	BIT(4)
+#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS	BIT(5)
+
 /* SBI spec version fields */
 #define SBI_SPEC_VERSION_DEFAULT	0x1
 #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
-- 
2.43.0


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2025-05-25  8:47 UTC|newest]

Thread overview: 108+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-25  8:46 [PATCH v4 00/23] Linux SBI MPXY and RPMI drivers Anup Patel
2025-05-25  8:46 ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 01/23] riscv: Add new error codes defined by SBI v3.0 Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-06-06 23:51   ` Atish Patra
2025-06-06 23:51     ` Atish Patra
2025-06-09  5:58     ` Anup Patel
2025-06-09  5:58       ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 02/23] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 03/23] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-25  8:46 ` Anup Patel [this message]
2025-05-25  8:46   ` [PATCH v4 04/23] RISC-V: Add defines for the SBI message proxy extension Anup Patel
2025-05-27  8:47   ` Andy Shevchenko
2025-05-27  8:47     ` Andy Shevchenko
2025-06-09  6:12     ` Anup Patel
2025-06-09  6:12       ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 05/23] mailbox: Add common header for RPMI messages sent via mailbox Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-27 11:16   ` Andy Shevchenko
2025-05-27 11:16     ` Andy Shevchenko
2025-06-09  8:48     ` Anup Patel
2025-06-09  8:48       ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 06/23] mailbox: Allow controller specific mapping using fwnode Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-27 11:41   ` Andy Shevchenko
2025-05-27 11:41     ` Andy Shevchenko
2025-06-09  9:10     ` Anup Patel
2025-06-09  9:10       ` Anup Patel
2025-06-09 19:53       ` Andy Shevchenko
2025-06-09 19:53         ` Andy Shevchenko
2025-05-25  8:46 ` [PATCH v4 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-28 10:52   ` Andy Shevchenko
2025-05-28 10:52     ` Andy Shevchenko
2025-06-09 12:29     ` Anup Patel
2025-06-09 12:29       ` Anup Patel
2025-06-09 20:04       ` Andy Shevchenko
2025-06-09 20:04         ` Andy Shevchenko
2025-06-10  4:35         ` Anup Patel
2025-06-10  4:35           ` Anup Patel
2025-06-10  9:55           ` Andy Shevchenko
2025-06-10  9:55             ` Andy Shevchenko
2025-06-11  5:21             ` Anup Patel
2025-06-11  5:21               ` Anup Patel
2025-06-11  8:23               ` Andy Shevchenko
2025-06-11  8:23                 ` Andy Shevchenko
2025-05-25  8:46 ` [PATCH v4 08/23] dt-bindings: clock: Add RPMI clock service message proxy bindings Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-30 16:28   ` Conor Dooley
2025-05-30 16:28     ` Conor Dooley
2025-06-10  5:00     ` Anup Patel
2025-06-10  5:00       ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 09/23] dt-bindings: clock: Add RPMI clock service controller bindings Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-30 16:41   ` Conor Dooley
2025-05-30 16:41     ` Conor Dooley
2025-06-10  5:20     ` Anup Patel
2025-06-10  5:20       ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 10/23] clk: Add clock driver for the RISC-V RPMI clock service group Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 11/23] dt-bindings: Add RPMI system MSI message proxy bindings Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-06-06 22:59   ` Atish Patra
2025-06-06 22:59     ` Atish Patra
2025-06-10  6:09     ` Anup Patel
2025-06-10  6:09       ` Anup Patel
2025-05-25  8:46 ` [PATCH v4 12/23] dt-bindings: Add RPMI system MSI interrupt controller bindings Anup Patel
2025-05-25  8:46   ` Anup Patel
2025-06-06 23:03   ` Atish Patra
2025-06-06 23:03     ` Atish Patra
2025-06-10  6:22     ` Anup Patel
2025-06-10  6:22       ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 13/23] irqchip: Add driver for the RPMI system MSI service group Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-27 11:33   ` Andy Shevchenko
2025-05-27 11:33     ` Andy Shevchenko
2025-06-10 11:03     ` Anup Patel
2025-06-10 11:03       ` Anup Patel
2025-06-11  8:22       ` Andy Shevchenko
2025-06-11  8:22         ` Andy Shevchenko
2025-05-25  8:47 ` [PATCH v4 14/23] ACPI: property: Refactor acpi_fwnode_get_reference_args() Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 15/23] ACPI: property: Add support for cells property Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 16/23] ACPI: scan: Update honor list for RPMI System MSI Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 17/23] ACPI: RISC-V: Create interrupt controller list in sorted order Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-28 11:05   ` Andy Shevchenko
2025-05-28 11:05     ` Andy Shevchenko
2025-06-10  4:42     ` Sunil V L
2025-06-10  4:42       ` Sunil V L
2025-06-11  8:21       ` Andy Shevchenko
2025-06-11  8:21         ` Andy Shevchenko
2025-05-25  8:47 ` [PATCH v4 18/23] ACPI: RISC-V: Add support to update gsi range Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 19/23] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 20/23] mailbox/riscv-sbi-mpxy: Add ACPI support Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 21/23] irqchip/riscv-rpmi-sysmsi: " Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 22/23] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Anup Patel
2025-05-25  8:47   ` Anup Patel
2025-05-25  8:47 ` [PATCH v4 23/23] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Anup Patel
2025-05-25  8:47   ` Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250525084710.1665648-5-apatel@ventanamicro.com \
    --to=apatel@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=anup@brainfault.org \
    --cc=atish.patra@linux.dev \
    --cc=brgl@bgdev.pl \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=jassisinghbrar@gmail.com \
    --cc=krzk+dt@kernel.org \
    --cc=lenb@kernel.org \
    --cc=leyfoon.tan@starfivetech.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=mika.westerberg@linux.intel.com \
    --cc=mturquette@baylibre.com \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=rafael@kernel.org \
    --cc=robh@kernel.org \
    --cc=rpathak@ventanamicro.com \
    --cc=samuel.holland@sifive.com \
    --cc=sboyd@kernel.org \
    --cc=sunilvl@ventanamicro.com \
    --cc=tglx@linutronix.de \
    --cc=ukleinek@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.