Re: [v10 PATCH 1/2] EDAC: Add EDAC driver for ARM Cortex A72 cores

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Tue, 27 May 2025 16:16:29 -0700
Vijay Balakrishna <vijayb@linux.microsoft.com> wrote:

> From: Sascha Hauer <s.hauer@pengutronix.de>
> 
> The driver is designed to support error detection and reporting for
> Cortex A72 cores, specifically within their L1 and L2 cache systems.
> The errors are detected by reading CPU/L2 memory error syndrome
> registers.
> 
> Unfortunately there is no robust way to inject errors into the caches,
> so this driver doesn't contain any code to actually test it. It has
> been tested though with code taken from an older version [1] of this
> driver. For reasons stated in thread [1], the error injection code is
> not suitable for mainline, so it is removed from the driver.
> 
> [1] https://lore.kernel.org/all/1521073067-24348-1-git-send-email-york.sun@nxp.com/#t
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Co-developed-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
> Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
I'm far from an expert on the EDAC side of things but generally this
looks good to me.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Note one comment inline that maybe it's worth adding a line
to the copyright notice given changes you've made?

Jonathan

> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index a8f2d8f6c894..136416f43b44 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -88,3 +88,4 @@ obj-$(CONFIG_EDAC_NPCM)			+= npcm_edac.o
>  obj-$(CONFIG_EDAC_ZYNQMP)		+= zynqmp_edac.o
>  obj-$(CONFIG_EDAC_VERSAL)		+= versal_edac.o
>  obj-$(CONFIG_EDAC_LOONGSON)		+= loongson_edac.o
> +obj-$(CONFIG_EDAC_CORTEX_A72)		+= edac_a72.o
> diff --git a/drivers/edac/edac_a72.c b/drivers/edac/edac_a72.c
> new file mode 100644
> index 000000000000..f23c28fba354
> --- /dev/null
> +++ b/drivers/edac/edac_a72.c
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Cortex A72 EDAC L1 and L2 cache error detection
> + *
> + * Copyright (c) 2020 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>

I'd argue that you've made enough changes to add an additional
copyright line.  Entirely up to you however!

> + *
> + * Based on Code from:
> + * Copyright (c) 2018, NXP Semiconductor
> + * Author: York Sun <york.sun@nxp.com>
> + */