From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 364D728ECC6 for ; Wed, 4 Jun 2025 14:32:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749047568; cv=none; b=CVd8JARSI94WsG/4SgPBfZI5BcZSoHyVpcEpuXMznQxNs2l+ONcL7oJUMbg3EmFtfky/RyfvW+JYSE2L47wwTgZ79uo71nzNG5CQNySe/L+CZNurzxSQp1UQ8QlTCyHCwB3KJny3+JB08Qg3/gjy/aF3jKu2XuprTMqIxwC8uDA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749047568; c=relaxed/simple; bh=9z8QudQWghDp5WMpvA3iQs3K28eMZKlUjQsez2q3whw=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tJTa5c9XnE59UcZufonaNSW9m410U4lnK6EWEC9l22nfa0KP9zZHTOAIZW+kcbvPYgIuHB3rzlv0TYMQpIRNHUpdpwMC7hC+o0+FrpUnmHIXVAbM6fIEa7djRcZlHDku2xvTu8k4lK0qHMr+v409+VaCfWHwo2kdb3LFDV9TQDs= ARC-Authentication-Results:i=1; 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x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500003.china.huawei.com (7.182.85.28) On Wed, 28 May 2025 12:07:26 +0100 Jonathan Cameron wrote: > Add a single complex case for aarch64 virt machine. > Given existing much more comprehensive tests for x86 cover the > common functionality, a single test should be enough to verify > that the aarch64 part continue to work. > > Tested-by: Itaru Kitayama > Signed-off-by: Jonathan Cameron > > --- > v14: Tags only. > --- > tests/qtest/cxl-test.c | 59 > ++++++++++++++++++++++++++++++++--------- tests/qtest/meson.build | > 1 + 2 files changed, 47 insertions(+), 13 deletions(-) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index a600331843..c7189d6222 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -19,6 +19,12 @@ > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G > " +#define QEMU_VIRT_2PXB_CMD \ > + "-machine virt,cxl=on -cpu max " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G > " + #define QEMU_RP \ > "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > > @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) > qtest_end(); > rmdir(tmpfs); > } > + > +static void cxl_virt_2pxb_4rp_4t3d(void) > +{ > + g_autoptr(GString) cmdline = g_string_new(NULL); > + char template[] = "/tmp/cxl-test-XXXXXX"; > + const char *tmpfs; > + > + tmpfs = mkdtemp(template); > + > + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, > + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, > + tmpfs, tmpfs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + rmdir(tmpfs); > +} > #endif /* CONFIG_POSIX */ > > int main(int argc, char **argv) > { > - g_test_init(&argc, &argv, NULL); > + const char *arch = qtest_get_arch(); > > - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > - qtest_add_func("/pci/cxl/pxb_x2_with_window", > cxl_2pxb_with_window); > - qtest_add_func("/pci/cxl/rp", cxl_root_port); > - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > + g_test_init(&argc, &argv, NULL); > + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { > + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > + qtest_add_func("/pci/cxl/pxb_with_window", > cxl_pxb_with_window); > + qtest_add_func("/pci/cxl/pxb_x2_with_window", > cxl_2pxb_with_window); > + qtest_add_func("/pci/cxl/rp", cxl_root_port); > + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > #ifdef CONFIG_POSIX > - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", > cxl_t3d_volatile_lsa); > - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > cxl_2pxb_4rp_4t3d); > + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > + qtest_add_func("/pci/cxl/type3_device_pmem", > cxl_t3d_persistent); > + qtest_add_func("/pci/cxl/type3_device_vmem", > cxl_t3d_volatile); > + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", > cxl_t3d_volatile_lsa); > + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > + cxl_2pxb_4rp_4t3d); > #endif > + } else if (strcmp(arch, "aarch64") == 0) { > +#ifdef CONFIG_POSIX > + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", > + cxl_virt_2pxb_4rp_4t3d); > +#endif > + } > + > return g_test_run(); > } > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 43e5a86699..3145c7b5fb 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -259,6 +259,7 @@ qtests_aarch64 = \ > (config_all_accel.has_key('CONFIG_TCG') and > \ > config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? > ['tpm-tis-i2c-test'] : []) + \ > (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : > []) + \ > + qtests_cxl + > \ ['arm-cpu-features', > 'numa-test', > 'boot-serial-test', Hi Jonathan, This patch does not apply on the latest master anymore. I think did a few days ago though. Not sure what's wrong. Thanks, Alireza From mboxrd@z Thu Jan 1 00:00:00 1970 Received: by 2002:a17:504:1b46:b0:1be9:327d:8ee3 with SMTP id t6csp4138934njh; Wed, 4 Jun 2025 07:33:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVerLveq9/EJxl86h9g4Ik3VdLAPtkVDCSFmq0qniaJovKiDt48K3PtiM3S6Te/H4+ar0SE+A49E4kGmQ==@linaro.org X-Google-Smtp-Source: AGHT+IFFN4zE9L2dpf1bWCndLoODuQiqqO6/IGkjVHoIMfIt4bMiqoT1AeRneLA+e9fooCDBa0+C X-Received: by 2002:a05:620a:3181:b0:7c5:5e05:df33 with SMTP id af79cd13be357-7d2198ef3c3mr449516185a.51.1749047602277; Wed, 04 Jun 2025 07:33:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1749047602; cv=none; d=google.com; s=arc-20240605; b=YWIobsONwqHAHIMJptrq2HlywoL05oMj4AoXIQyGwsPZWDxnjujvzQ4L1aeZhctGkg ibvP1Harof8EEJ/A8gcM9EoX0mMIbendHtmvEGlM2E/QmVLjKglQADTF9RmB5o7TxQ9E 2iAX2dO40Ye6PMTZFCXq2qN4wXki4oHFHFU8SmFPz6ygQzaptPYdL5/C/GrmB7Sxd539 xJkMkxfn2NGCc/rR69ROGKvoJSrTrbjU3LluYHbmKhoGqJZ8QYiz0DHEVhxhnqyy6yrm mAxEyBMnzp2o43xUxXyAa1UhK1HDlQNirbPar7mbAv+0DW+OyDKkgqjpzh5sKhwLbS4I sNqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:from:reply-to:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:organization:references :in-reply-to:message-id:subject:cc:to:date; bh=SLmTshJPJv0Pe+jwxL6MVWrO2MnnGtBHromxE18Q29U=; fh=tua/CDVJZ+sbrFft9hFgWdrPa6BmNXQR1cvssXCUvV8=; b=jodPsqFNlx1l6TkXycITj13V0ZQFnSBOFj0RK5eOF1IBSvcmzukA/j9PaI1xr0SlpA TYV+3ik1CMOrcCPBVGT62mnusYuxephouJYrazpVSicx6aw0WK4SwlRIWewvdJNI9OiK 9AJMqbwPZ135j5cPEXcc5RtcIJJBDZEeIbFrTHVEshC5TncbBCUkF3ArppiR+iYve72I U+nkV5WKpE+buBTlSjbQadUnGncI9Qsh/hsYn8zD1KFjH3bxmu5toXox733ECtf5So5m NQkXeKIBUDb4gNP6XbUpF20trCWYbbs46iLsuV32dtVfmDiwg4ZutQO77QZPPc3yH1KL o+dw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 04 Jun 2025 10:32:59 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uMpAm-0005tU-Cc; Wed, 04 Jun 2025 10:32:59 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bC95n2HQGz6K99W; Wed, 4 Jun 2025 22:32:29 +0800 (CST) Received: from frapeml500003.china.huawei.com (unknown [7.182.85.28]) by mail.maildlp.com (Postfix) with ESMTPS id 8E2E71400D9; Wed, 4 Jun 2025 22:32:42 +0800 (CST) Received: from localhost (10.203.177.99) by frapeml500003.china.huawei.com (7.182.85.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 4 Jun 2025 16:32:41 +0200 Date: Wed, 4 Jun 2025 15:32:37 +0100 To: Jonathan Cameron CC: , Fan Ni , Peter Maydell , , , , Yuquan Wang , "Itaru Kitayama" , Philippe =?ISO-8859-1?Q?Mathieu-Daud?= =?ISO-8859-1?Q?=E9?= , Alireza Sanaee Subject: Re: [PATCH v14 5/5] qtest/cxl: Add aarch64 virt test for CXL Message-ID: <20250604153051.0000190c@huawei.com> In-Reply-To: <20250528110726.226389-6-Jonathan.Cameron@huawei.com> References: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> <20250528110726.226389-6-Jonathan.Cameron@huawei.com> Organization: Huawei X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.99] X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500003.china.huawei.com (7.182.85.28) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alireza Sanaee From: Alireza Sanaee via Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 819GAzpTgwDy On Wed, 28 May 2025 12:07:26 +0100 Jonathan Cameron wrote: > Add a single complex case for aarch64 virt machine. > Given existing much more comprehensive tests for x86 cover the > common functionality, a single test should be enough to verify > that the aarch64 part continue to work. > > Tested-by: Itaru Kitayama > Signed-off-by: Jonathan Cameron > > --- > v14: Tags only. > --- > tests/qtest/cxl-test.c | 59 > ++++++++++++++++++++++++++++++++--------- tests/qtest/meson.build | > 1 + 2 files changed, 47 insertions(+), 13 deletions(-) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index a600331843..c7189d6222 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -19,6 +19,12 @@ > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G > " +#define QEMU_VIRT_2PXB_CMD \ > + "-machine virt,cxl=on -cpu max " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G > " + #define QEMU_RP \ > "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > > @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) > qtest_end(); > rmdir(tmpfs); > } > + > +static void cxl_virt_2pxb_4rp_4t3d(void) > +{ > + g_autoptr(GString) cmdline = g_string_new(NULL); > + char template[] = "/tmp/cxl-test-XXXXXX"; > + const char *tmpfs; > + > + tmpfs = mkdtemp(template); > + > + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, > + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, > + tmpfs, tmpfs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + rmdir(tmpfs); > +} > #endif /* CONFIG_POSIX */ > > int main(int argc, char **argv) > { > - g_test_init(&argc, &argv, NULL); > + const char *arch = qtest_get_arch(); > > - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > - qtest_add_func("/pci/cxl/pxb_x2_with_window", > cxl_2pxb_with_window); > - qtest_add_func("/pci/cxl/rp", cxl_root_port); > - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > + g_test_init(&argc, &argv, NULL); > + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { > + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > + qtest_add_func("/pci/cxl/pxb_with_window", > cxl_pxb_with_window); > + qtest_add_func("/pci/cxl/pxb_x2_with_window", > cxl_2pxb_with_window); > + qtest_add_func("/pci/cxl/rp", cxl_root_port); > + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > #ifdef CONFIG_POSIX > - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", > cxl_t3d_volatile_lsa); > - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > cxl_2pxb_4rp_4t3d); > + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > + qtest_add_func("/pci/cxl/type3_device_pmem", > cxl_t3d_persistent); > + qtest_add_func("/pci/cxl/type3_device_vmem", > cxl_t3d_volatile); > + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", > cxl_t3d_volatile_lsa); > + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > + cxl_2pxb_4rp_4t3d); > #endif > + } else if (strcmp(arch, "aarch64") == 0) { > +#ifdef CONFIG_POSIX > + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", > + cxl_virt_2pxb_4rp_4t3d); > +#endif > + } > + > return g_test_run(); > } > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 43e5a86699..3145c7b5fb 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -259,6 +259,7 @@ qtests_aarch64 = \ > (config_all_accel.has_key('CONFIG_TCG') and > \ > config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? > ['tpm-tis-i2c-test'] : []) + \ > (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : > []) + \ > + qtests_cxl + > \ ['arm-cpu-features', > 'numa-test', > 'boot-serial-test', Hi Jonathan, This patch does not apply on the latest master anymore. I think did a few days ago though. Not sure what's wrong. Thanks, Alireza From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33AF5C5B543 for ; Wed, 4 Jun 2025 14:34:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uMpAv-0001mz-NL; Wed, 04 Jun 2025 10:33:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uMpAp-0001lK-FD; Wed, 04 Jun 2025 10:32:59 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uMpAm-0005tU-Cc; Wed, 04 Jun 2025 10:32:59 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bC95n2HQGz6K99W; Wed, 4 Jun 2025 22:32:29 +0800 (CST) Received: from frapeml500003.china.huawei.com (unknown [7.182.85.28]) by mail.maildlp.com (Postfix) with ESMTPS id 8E2E71400D9; Wed, 4 Jun 2025 22:32:42 +0800 (CST) Received: from localhost (10.203.177.99) by frapeml500003.china.huawei.com (7.182.85.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 4 Jun 2025 16:32:41 +0200 Date: Wed, 4 Jun 2025 15:32:37 +0100 To: Jonathan Cameron CC: , Fan Ni , Peter Maydell , , , , Yuquan Wang , "Itaru Kitayama" , Philippe =?ISO-8859-1?Q?Mathieu-Daud?= =?ISO-8859-1?Q?=E9?= , Alireza Sanaee Subject: Re: [PATCH v14 5/5] qtest/cxl: Add aarch64 virt test for CXL Message-ID: <20250604153051.0000190c@huawei.com> In-Reply-To: <20250528110726.226389-6-Jonathan.Cameron@huawei.com> References: <20250528110726.226389-1-Jonathan.Cameron@huawei.com> <20250528110726.226389-6-Jonathan.Cameron@huawei.com> Organization: Huawei X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.99] X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500003.china.huawei.com (7.182.85.28) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alireza Sanaee From: Alireza Sanaee via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 28 May 2025 12:07:26 +0100 Jonathan Cameron wrote: > Add a single complex case for aarch64 virt machine. > Given existing much more comprehensive tests for x86 cover the > common functionality, a single test should be enough to verify > that the aarch64 part continue to work. > > Tested-by: Itaru Kitayama > Signed-off-by: Jonathan Cameron > > --- > v14: Tags only. > --- > tests/qtest/cxl-test.c | 59 > ++++++++++++++++++++++++++++++++--------- tests/qtest/meson.build | > 1 + 2 files changed, 47 insertions(+), 13 deletions(-) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index a600331843..c7189d6222 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -19,6 +19,12 @@ > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G > " +#define QEMU_VIRT_2PXB_CMD \ > + "-machine virt,cxl=on -cpu max " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G > " + #define QEMU_RP \ > "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > > @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) > qtest_end(); > rmdir(tmpfs); > } > + > +static void cxl_virt_2pxb_4rp_4t3d(void) > +{ > + g_autoptr(GString) cmdline = g_string_new(NULL); > + char template[] = "/tmp/cxl-test-XXXXXX"; > + const char *tmpfs; > + > + tmpfs = mkdtemp(template); > + > + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, > + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, > + tmpfs, tmpfs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + rmdir(tmpfs); > +} > #endif /* CONFIG_POSIX */ > > int main(int argc, char **argv) > { > - g_test_init(&argc, &argv, NULL); > + const char *arch = qtest_get_arch(); > > - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > - qtest_add_func("/pci/cxl/pxb_x2_with_window", > cxl_2pxb_with_window); > - qtest_add_func("/pci/cxl/rp", cxl_root_port); > - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > + g_test_init(&argc, &argv, NULL); > + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { > + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > + qtest_add_func("/pci/cxl/pxb_with_window", > cxl_pxb_with_window); > + qtest_add_func("/pci/cxl/pxb_x2_with_window", > cxl_2pxb_with_window); > + qtest_add_func("/pci/cxl/rp", cxl_root_port); > + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > #ifdef CONFIG_POSIX > - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", > cxl_t3d_volatile_lsa); > - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > cxl_2pxb_4rp_4t3d); > + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > + qtest_add_func("/pci/cxl/type3_device_pmem", > cxl_t3d_persistent); > + qtest_add_func("/pci/cxl/type3_device_vmem", > cxl_t3d_volatile); > + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", > cxl_t3d_volatile_lsa); > + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > + cxl_2pxb_4rp_4t3d); > #endif > + } else if (strcmp(arch, "aarch64") == 0) { > +#ifdef CONFIG_POSIX > + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", > + cxl_virt_2pxb_4rp_4t3d); > +#endif > + } > + > return g_test_run(); > } > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 43e5a86699..3145c7b5fb 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -259,6 +259,7 @@ qtests_aarch64 = \ > (config_all_accel.has_key('CONFIG_TCG') and > \ > config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? > ['tpm-tis-i2c-test'] : []) + \ > (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : > []) + \ > + qtests_cxl + > \ ['arm-cpu-features', > 'numa-test', > 'boot-serial-test', Hi Jonathan, This patch does not apply on the latest master anymore. I think did a few days ago though. Not sure what's wrong. Thanks, Alireza