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[209.51.188.17]) by mx.google.com with ESMTPS id a1e0cc1a2514c-87f1ec1a2bcsi889026241.77.2025.06.16.04.06.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Jun 2025 04:06:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uR7fI-00074j-RG; Mon, 16 Jun 2025 07:06:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uR7fG-00073p-CW; Mon, 16 Jun 2025 07:06:10 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uR7fD-00036N-Bo; Mon, 16 Jun 2025 07:06:10 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bLRvb4Csfz6L5NM; Mon, 16 Jun 2025 19:03:55 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 9C9FA140447; Mon, 16 Jun 2025 19:06:02 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 16 Jun 2025 13:06:01 +0200 Date: Mon, 16 Jun 2025 12:05:59 +0100 To: Shameer Kolothum , CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 6/7] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Message-ID: <20250616120545.000017d5@huawei.com> In-Reply-To: <20250613144449.60156-7-shameerali.kolothum.thodi@huawei.com> References: <20250613144449.60156-1-shameerali.kolothum.thodi@huawei.com> <20250613144449.60156-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.66] X-ClientProxiedBy: lhrpeml100005.china.huawei.com (7.191.160.25) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: XidxT3Oo+dcq On Fri, 13 Jun 2025 15:44:48 +0100 Shameer Kolothum wrote: > Allow cold-plug of smmuv3 device to virt if there is no machine > wide legacy smmuv3 or a virtio-iommu is specified. > > Device tree support for new smmuv3 dev is limited to the case where > it is associated with the default pcie.0 RC. > > Tested-by: Nathan Chen > Signed-off-by: Shameer Kolothum Looks good to me. Reviewed-by: Jonathan Cameron > --- > hw/arm/smmuv3.c | 2 ++ > hw/arm/virt.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ > hw/core/sysbus-fdt.c | 3 +++ > 3 files changed, 52 insertions(+) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index ab67972353..bcf8af8dc7 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -1996,6 +1996,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) > device_class_set_parent_realize(dc, smmu_realize, > &c->parent_realize); > device_class_set_props(dc, smmuv3_properties); > + dc->hotpluggable = false; > + dc->user_creatable = true; > } > > static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index eeace4754d..3be007d87c 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -56,6 +56,7 @@ > #include "qemu/cutils.h" > #include "qemu/error-report.h" > #include "qemu/module.h" > +#include "hw/pci/pci_bus.h" > #include "hw/pci-host/gpex.h" > #include "hw/virtio/virtio-pci.h" > #include "hw/core/sysbus-fdt.h" > @@ -1443,6 +1444,28 @@ static void create_smmuv3_dt_bindings(const VirtMachineState *vms, hwaddr base, > g_free(node); > } > > +static void create_smmuv3_dev_dtb(VirtMachineState *vms, > + DeviceState *dev, PCIBus *bus) > +{ > + PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); > + SysBusDevice *sbdev = SYS_BUS_DEVICE(dev); > + int irq = platform_bus_get_irqn(pbus, sbdev, 0); > + hwaddr base = platform_bus_get_mmio_addr(pbus, sbdev, 0); > + MachineState *ms = MACHINE(vms); > + > + if (strcmp("pcie.0", bus->qbus.name)) { > + warn_report("SMMUv3 device only supported with pcie.0 for DT"); > + return; > + } > + base += vms->memmap[VIRT_PLATFORM_BUS].base; > + irq += vms->irqmap[VIRT_PLATFORM_BUS]; > + > + vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); > + create_smmuv3_dt_bindings(vms, base, SMMU_IO_LEN, irq); > + qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", > + 0x0, vms->iommu_phandle, 0x0, 0x10000); > +} > + > static void create_smmu(const VirtMachineState *vms, > PCIBus *bus) > { > @@ -2931,6 +2954,13 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, > qlist_append_str(reserved_regions, resv_prop_str); > qdev_prop_set_array(dev, "reserved-regions", reserved_regions); > g_free(resv_prop_str); > + } else if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) { > + if (vms->legacy_smmuv3_present || vms->iommu == VIRT_IOMMU_VIRTIO) { > + error_setg(errp, "virt machine already has %s set. " > + "Doesn't support incompatible iommus", > + (vms->legacy_smmuv3_present) ? > + "iommu=smmuv3" : "virtio-iommu"); > + } > } > } > > @@ -2954,6 +2984,22 @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, > virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); > } > > + if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) { > + if (!vms->legacy_smmuv3_present && vms->platform_bus_dev) { > + PCIBus *bus; > + > + bus = PCI_BUS(object_property_get_link(OBJECT(dev), "primary-bus", > + &error_abort)); > + if (pci_bus_bypass_iommu(bus)) { > + error_setg(errp, "Bypass option cannot be set for SMMUv3 " > + "associated PCIe RC"); > + return; > + } > + > + create_smmuv3_dev_dtb(vms, dev, bus); > + } > + } > +