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From: Pravin Pathak <pravin.pathak@intel.com>
To: dev@dpdk.org
Cc: jerinj@marvell.com, mike.ximing.chen@intel.com,
	bruce.richardson@intel.com, thomas@monjalon.net,
	david.marchand@redhat.com, nipun.gupta@amd.com,
	chenbox@nvidia.com, tirthendu.sarkar@intel.com,
	Pravin Pathak <pravin.pathak@intel.com>,
	stable@dpdk.org
Subject: [PATCH v3 1/7] event/dlb2: fix addresses deq failure when CQ depth <= 16
Date: Tue, 17 Jun 2025 13:26:24 -0500	[thread overview]
Message-ID: <20250617182631.257612-2-pravin.pathak@intel.com> (raw)
In-Reply-To: <20250617182631.257612-1-pravin.pathak@intel.com>

When application configures a DIR port with CQ depth less than 8, DLB PMD
sets port's cq_depth as 8 and token reservation is used to make the
effective cq_depth smaller. However, while setting port's cq_depth_mask
application configured CQ depth was used resulting in reading incorrect
cachelines while dequeuing. Use PMD calculated CQ depth for cq_depth_mask
calculation.

Fixes: 3a6d0c04e7fb3e ("event/dlb2: add port setup")
Cc: stable@dpdk.org

Signed-off-by: Pravin Pathak <pravin.pathak@intel.com>
Signed-off-by: Tirthendu Sarkar <tirthendu.sarkar@intel.com>
---
 drivers/event/dlb2/dlb2.c       | 4 ++--
 drivers/event/dlb2/pf/dlb2_pf.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index 286241ea41..a0e673b96b 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -1951,9 +1951,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
 	qm_port->cq_idx_unmasked = 0;
 
 	if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
-		qm_port->cq_depth_mask = (cfg.cq_depth * 4) - 1;
+		qm_port->cq_depth_mask = (qm_port->cq_depth * 4) - 1;
 	else
-		qm_port->cq_depth_mask = cfg.cq_depth - 1;
+		qm_port->cq_depth_mask = qm_port->cq_depth - 1;
 
 	qm_port->gen_bit_shift = rte_popcount32(qm_port->cq_depth_mask);
 	/* starting value of gen bit - it toggles at wrap time */
diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
index ed4e6e424c..31b5487d85 100644
--- a/drivers/event/dlb2/pf/dlb2_pf.c
+++ b/drivers/event/dlb2/pf/dlb2_pf.c
@@ -400,7 +400,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,
 	/* Calculate the port memory required, and round up to the nearest
 	 * cache line.
 	 */
-	alloc_sz = cfg->cq_depth * qe_sz;
+	alloc_sz = RTE_MAX(cfg->cq_depth, DLB2_MIN_HARDWARE_CQ_DEPTH) * qe_sz;
 	alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
 
 	port_base = dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz,
-- 
2.39.1


  reply	other threads:[~2025-06-17 18:26 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-09  4:23 [PATCH v1 0/7] event/dlb2: dlb2 hw resource management Pravin Pathak
2025-05-09  4:23 ` [PATCH v1 1/7] event/dlb2: addresses deq failure when CQ depth <= 16 Pravin Pathak
2025-05-09  4:23 ` [PATCH v1 2/7] event/dlb2: changes to correctly validate COS ID arguments Pravin Pathak
2025-05-09  4:23 ` [PATCH v1 3/7] event/dlb2: return 96 single link ports for DLB2.5 Pravin Pathak
2025-05-09  4:23 ` [PATCH v1 4/7] event/dlb2: support managing history list resource Pravin Pathak
2025-05-27  5:50   ` [EXTERNAL] " Jerin Jacob
     [not found]   ` <BY3PR18MB4785C4D398C95857C86D67F2C864A@BY3PR18MB4785.namprd18.prod.outlook.com>
2025-05-27 13:16     ` Thomas Monjalon
2025-05-09  4:23 ` [PATCH v1 5/7] event/dlb2: avoid credit release race condition Pravin Pathak
2025-05-09  4:24 ` [PATCH v1 6/7] event/dlb2: update qid depth xstat in vector path Pravin Pathak
2025-05-09  4:24 ` [PATCH v1 7/7] event/dlb2: fix default credits in dlb2_eventdev_info_get() Pravin Pathak
2025-06-03 18:05 ` [PATCH v2 0/7] event/dlb2: dlb2 hw resource management Pravin Pathak
2025-06-03 18:05   ` [PATCH v2 1/7] event/dlb2: addresses deq failure when CQ depth <= 16 Pravin Pathak
2025-06-04  8:58     ` Jerin Jacob
2025-06-03 18:05   ` [PATCH v2 2/7] event/dlb2: changes to correctly validate COS ID arguments Pravin Pathak
2025-06-03 18:05   ` [PATCH v2 3/7] event/dlb2: return 96 single link ports for DLB2.5 Pravin Pathak
2025-06-03 18:05   ` [PATCH v2 4/7] event/dlb2: support managing history list resource Pravin Pathak
2025-06-03 18:05   ` [PATCH v2 5/7] event/dlb2: avoid credit release race condition Pravin Pathak
2025-06-03 18:05   ` [PATCH v2 6/7] event/dlb2: update qid depth xstat in vector path Pravin Pathak
2025-06-03 18:05   ` [PATCH v2 7/7] event/dlb2: return default credits based on HW version Pravin Pathak
2025-06-17 18:26 ` [PATCH v3 0/7] event/dlb2: dlb2 hw resource management Pravin Pathak
2025-06-17 18:26   ` Pravin Pathak [this message]
2025-06-17 18:26   ` [PATCH v3 2/7] event/dlb2: fix validaton of LDB port COS ID arguments Pravin Pathak
2025-06-17 18:26   ` [PATCH v3 3/7] event/dlb2: fix num single link ports for DLB2.5 Pravin Pathak
2025-06-17 18:26   ` [PATCH v3 4/7] event/dlb2: support managing history list resource Pravin Pathak
2025-06-18  9:26     ` Jerin Jacob
2025-06-18 22:58       ` Pathak, Pravin
2025-06-17 18:26   ` [PATCH v3 5/7] event/dlb2: fix to avoid credit release race condition Pravin Pathak
2025-06-17 18:26   ` [PATCH v3 6/7] event/dlb2: fix qid depth xstat in vector path Pravin Pathak
2025-06-17 18:26   ` [PATCH v3 7/7] event/dlb2: fix default credits based on HW version Pravin Pathak
2025-06-19  4:03 ` [PATCH v4 0/7] event/dlb2: dlb2 hw resource management Pravin Pathak
2025-06-19  4:03   ` [PATCH v4 1/7] event/dlb2: fix addresses deq failure when CQ depth <= 16 Pravin Pathak
2025-06-19  4:03   ` [PATCH v4 2/7] event/dlb2: fix validaton of LDB port COS ID arguments Pravin Pathak
2025-06-19  4:03   ` [PATCH v4 3/7] event/dlb2: fix num single link ports for DLB2.5 Pravin Pathak
2025-06-19  4:03   ` [PATCH v4 4/7] event/dlb2: support managing history list resource Pravin Pathak
2025-06-19  4:03   ` [PATCH v4 5/7] event/dlb2: fix to avoid credit release race condition Pravin Pathak
2025-06-19  4:03   ` [PATCH v4 6/7] event/dlb2: fix qid depth xstat in vector path Pravin Pathak
2025-06-19  4:03   ` [PATCH v4 7/7] event/dlb2: fix default credits based on HW version Pravin Pathak
2025-06-19  8:37     ` Jerin Jacob

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