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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4a72a518bcasi140163351cf.534.2025.06.18.03.38.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Jun 2025 03:38:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRqBg-0006Eo-T6; Wed, 18 Jun 2025 06:38:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRqBd-0006EZ-6P; Wed, 18 Jun 2025 06:38:33 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRqBa-0001Xz-2v; Wed, 18 Jun 2025 06:38:32 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bMgBd1f9wz6K7kc; Wed, 18 Jun 2025 18:36:09 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id DF06A140119; Wed, 18 Jun 2025 18:38:21 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 18 Jun 2025 12:38:21 +0200 Date: Wed, 18 Jun 2025 11:38:19 +0100 To: Shameerali Kolothum Thodi CC: Eric Auger , Linuxarm , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "ddutile@redhat.com" , "berrange@redhat.com" , "imammedo@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , "Wangzhou (B)" , jiangkunkun , "zhangfei.gao@linaro.org" Subject: Re: [PATCH v4 1/7] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Message-ID: <20250618113819.0000054b@huawei.com> In-Reply-To: <49d4c4b73e9a44a783332ddfe9a2fbdf@huawei.com> References: <20250613144449.60156-1-shameerali.kolothum.thodi@huawei.com> <20250613144449.60156-2-shameerali.kolothum.thodi@huawei.com> <20250616112019.00003bce@huawei.com> <20250617175247.00007d43@huawei.com> <49d4c4b73e9a44a783332ddfe9a2fbdf@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.66] X-ClientProxiedBy: lhrpeml500003.china.huawei.com (7.191.162.67) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: VVo95X8AAuql On Wed, 18 Jun 2025 09:35:35 +0100 Shameerali Kolothum Thodi wrote: > > -----Original Message----- > > From: Jonathan Cameron > > Sent: Tuesday, June 17, 2025 5:53 PM > > To: Eric Auger > > Cc: Shameerali Kolothum Thodi > > ; Linuxarm > > ; qemu-arm@nongnu.org; qemu- > > devel@nongnu.org; peter.maydell@linaro.org; jgg@nvidia.com; > > nicolinc@nvidia.com; ddutile@redhat.com; berrange@redhat.com; > > imammedo@redhat.com; nathanc@nvidia.com; mochs@nvidia.com; > > smostafa@google.com; Wangzhou (B) ; > > jiangkunkun ; zhangfei.gao@linaro.org > > Subject: Re: [PATCH v4 1/7] hw/arm/smmu-common: Check SMMU has PCIe > > Root Complex association > >=20 > > On Tue, 17 Jun 2025 09:49:54 +0200 > > Eric Auger wrote: > > =20 > > > On 6/16/25 12:20 PM, Jonathan Cameron wrote: =20 > > > > On Fri, 13 Jun 2025 15:44:43 +0100 > > > > Shameer Kolothum wrote: > > > > =20 > > > >> Although this change does not affect functionality at present, it = is =20 > > > > Patch title says PCIe. This check is vs PCI host bridge. > > > > > > > > No idea which one you wanted, but if it is PCIe needs to be > > > > TYPC_PCIE_HOST_BRIDGE from pcie_host.h not the pci_host.h one > > > > I think. =20 > > > I think we need TYPE_PCI_HOST_BRIDGE as we want to check against pxb > > > > > > pci-bridge/pci_expander_bridge.c:=A0=A0=A0 .parent=A0=A0=A0=A0=A0=A0= =A0 =3D =20 > > TYPE_PCI_HOST_BRIDGE, > >=20 > > Hmm. That's awkward and I'd forgotten that wrinkle. > > Need a stronger test but which one? The PXB root bus has a parent of > > TYPE_PCIE_BUS. Maybe we can check that? =20 >=20 > Ok. How about we do something like below? >=20 >=20 > @@ -925,6 +926,7 @@ static void smmu_base_realize(DeviceState *dev, > Error **errp) > { > SMMUState *s =3D ARM_SMMU(dev); > SMMUBaseClass *sbc =3D ARM_SMMU_GET_CLASS(dev); > + PCIBus *pci_bus =3D s->primary_bus; > Error *local_err =3D NULL; >=20 > sbc->parent_realize(dev, &local_err); > @@ -937,10 +939,31 @@ static void smmu_base_realize(DeviceState *dev, > Error **errp) > g_free, g_free); > s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL); >=20 > - if (s->primary_bus) { > - pci_setup_iommu(s->primary_bus, &smmu_ops, s); > - } else { > + if (!pci_bus) { > error_setg(errp, "SMMU is not attached to any PCI bus!"); > + return; > + } > + > + /* > + * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based= extra > + * root complexes to be associated with SMMU. > + */ > + if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && > + object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDG= E)) { > + /* > + * For pxb-pcie, parent_dev will be set. Make sure it is > + * pxb-pcie indeed. > + */ > + if (pci_bus->parent_dev) { > + if (!object_dynamic_cast(OBJECT(pci_bus), "pxb-pcie-bus")) { > + error_setg(errp, "SMMU is not attached to pxb-pcie bus!"= ); > + return; > + } > + } > + pci_setup_iommu(pci_bus, &smmu_ops, s); > + } else { > + error_setg(errp, "SMMU should be attached to a default PCIe > root complex" > + "(pcie.0) or a pxb-pcie based root complex"); > } > } >=20 > Please let me know if this is good enough or not. LGTM >=20 > Thanks, > Shameer From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C94BAC7115A for ; Wed, 18 Jun 2025 10:39:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRqBg-0006FS-Ad; Wed, 18 Jun 2025 06:38:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRqBd-0006EZ-6P; Wed, 18 Jun 2025 06:38:33 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRqBa-0001Xz-2v; Wed, 18 Jun 2025 06:38:32 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bMgBd1f9wz6K7kc; Wed, 18 Jun 2025 18:36:09 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id DF06A140119; Wed, 18 Jun 2025 18:38:21 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 18 Jun 2025 12:38:21 +0200 Date: Wed, 18 Jun 2025 11:38:19 +0100 To: Shameerali Kolothum Thodi CC: Eric Auger , Linuxarm , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "ddutile@redhat.com" , "berrange@redhat.com" , "imammedo@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , "Wangzhou (B)" , jiangkunkun , "zhangfei.gao@linaro.org" Subject: Re: [PATCH v4 1/7] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Message-ID: <20250618113819.0000054b@huawei.com> In-Reply-To: <49d4c4b73e9a44a783332ddfe9a2fbdf@huawei.com> References: <20250613144449.60156-1-shameerali.kolothum.thodi@huawei.com> <20250613144449.60156-2-shameerali.kolothum.thodi@huawei.com> <20250616112019.00003bce@huawei.com> <20250617175247.00007d43@huawei.com> <49d4c4b73e9a44a783332ddfe9a2fbdf@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.66] X-ClientProxiedBy: lhrpeml500003.china.huawei.com (7.191.162.67) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 18 Jun 2025 09:35:35 +0100 Shameerali Kolothum Thodi wrote: > > -----Original Message----- > > From: Jonathan Cameron > > Sent: Tuesday, June 17, 2025 5:53 PM > > To: Eric Auger > > Cc: Shameerali Kolothum Thodi > > ; Linuxarm > > ; qemu-arm@nongnu.org; qemu- > > devel@nongnu.org; peter.maydell@linaro.org; jgg@nvidia.com; > > nicolinc@nvidia.com; ddutile@redhat.com; berrange@redhat.com; > > imammedo@redhat.com; nathanc@nvidia.com; mochs@nvidia.com; > > smostafa@google.com; Wangzhou (B) ; > > jiangkunkun ; zhangfei.gao@linaro.org > > Subject: Re: [PATCH v4 1/7] hw/arm/smmu-common: Check SMMU has PCIe > > Root Complex association > >=20 > > On Tue, 17 Jun 2025 09:49:54 +0200 > > Eric Auger wrote: > > =20 > > > On 6/16/25 12:20 PM, Jonathan Cameron wrote: =20 > > > > On Fri, 13 Jun 2025 15:44:43 +0100 > > > > Shameer Kolothum wrote: > > > > =20 > > > >> Although this change does not affect functionality at present, it = is =20 > > > > Patch title says PCIe. This check is vs PCI host bridge. > > > > > > > > No idea which one you wanted, but if it is PCIe needs to be > > > > TYPC_PCIE_HOST_BRIDGE from pcie_host.h not the pci_host.h one > > > > I think. =20 > > > I think we need TYPE_PCI_HOST_BRIDGE as we want to check against pxb > > > > > > pci-bridge/pci_expander_bridge.c:=A0=A0=A0 .parent=A0=A0=A0=A0=A0=A0= =A0 =3D =20 > > TYPE_PCI_HOST_BRIDGE, > >=20 > > Hmm. That's awkward and I'd forgotten that wrinkle. > > Need a stronger test but which one? The PXB root bus has a parent of > > TYPE_PCIE_BUS. Maybe we can check that? =20 >=20 > Ok. How about we do something like below? >=20 >=20 > @@ -925,6 +926,7 @@ static void smmu_base_realize(DeviceState *dev, > Error **errp) > { > SMMUState *s =3D ARM_SMMU(dev); > SMMUBaseClass *sbc =3D ARM_SMMU_GET_CLASS(dev); > + PCIBus *pci_bus =3D s->primary_bus; > Error *local_err =3D NULL; >=20 > sbc->parent_realize(dev, &local_err); > @@ -937,10 +939,31 @@ static void smmu_base_realize(DeviceState *dev, > Error **errp) > g_free, g_free); > s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL); >=20 > - if (s->primary_bus) { > - pci_setup_iommu(s->primary_bus, &smmu_ops, s); > - } else { > + if (!pci_bus) { > error_setg(errp, "SMMU is not attached to any PCI bus!"); > + return; > + } > + > + /* > + * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based= extra > + * root complexes to be associated with SMMU. > + */ > + if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && > + object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDG= E)) { > + /* > + * For pxb-pcie, parent_dev will be set. Make sure it is > + * pxb-pcie indeed. > + */ > + if (pci_bus->parent_dev) { > + if (!object_dynamic_cast(OBJECT(pci_bus), "pxb-pcie-bus")) { > + error_setg(errp, "SMMU is not attached to pxb-pcie bus!"= ); > + return; > + } > + } > + pci_setup_iommu(pci_bus, &smmu_ops, s); > + } else { > + error_setg(errp, "SMMU should be attached to a default PCIe > root complex" > + "(pcie.0) or a pxb-pcie based root complex"); > } > } >=20 > Please let me know if this is good enough or not. LGTM >=20 > Thanks, > Shameer