From mboxrd@z Thu Jan 1 00:00:00 1970 Received: by 2002:a17:505:8ed0:b0:1be9:327d:8ee3 with SMTP id kh16csp76111njc; Wed, 18 Jun 2025 23:43:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV+QRZYGKHuj0FP8J4ltCI/DgP3FP98DqBWeyc4klk2eaphFZ3Yitl4/DwsU5tdTWQIiifCAJD+VDeIuw==@linaro.org X-Google-Smtp-Source: AGHT+IELxfXwWlAxfpOFU7io87zyopNAl+8JW6aTiHLnr1Gv/C26ZO4SRwNJIo3Vh15xp1cgACRC X-Received: by 2002:a05:620a:319b:b0:7c7:a5cb:2b65 with SMTP id af79cd13be357-7d3c6cdeed5mr2993443985a.26.1750315385282; Wed, 18 Jun 2025 23:43:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1750315385; cv=none; d=google.com; s=arc-20240605; b=Y0PlANsR14hbGWLVVDuJUSmAuyVY/6lnwr84k5eMey8uDbUdpi2eMEsxIJQNMGKOtN bMAsZZ+fouF1Ibme5MM6s2N3LpEkmhEPWR/afEsKeGhVrn4vgtR+6Q/eVkXDkiI/HEhp hD9Wsq4qbGy4GuMSep2t9hFe6dMqXAKk4K5b95iPYIvkv5Q0jxGQWIrCxjMwiyNv4gaC Ac+LoyNvST654t1j4u/9TO53IgfOkN0cTidjmxIrmV78faxjQE1lQl5bmFNsXM/Fknps uDKRs3VDzwCVaSukrDTE8JcuWSW6pCISboDqXISpEE2qfaycJb272GsVi953sz26JQUY xBXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:from:reply-to:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to; bh=QGkzt2OXyvvXTV/gAiilby18HQC1XzfXzh41je8QjG8=; fh=3E+GgkJ59sv88GyUpaKWpV4DoJlJz+B5Ev7H4uQXan0=; b=FkMMl25DRZzf7+Y0Jl877XR486TH7xEeeO2gJH/ozwCSD25Sf/hneZXDHVUGWkmqEW 0brDtWnUcnWoSvu7sKANWdYMRAUKAN3b2+B5tepC1DWePO7bTjQrdOPkqHnloyfexzdV bk5sUL2GAwb4NhLd1qIB7z5y7UXqxY73gOTFUdpsJjfcNJv0HnB5+bfBfh2m0/OQFQKP AuJKVxE3ytwQxg5exbeL8VBM04cNPrkm/kulHo0Uh/HWaXVipJk66s2c9gFdEOLVXEl1 sD58yHdDpJCCmwZ6NTM7wI9xQK5v0r6TQInxdfjA8XnfYO7n0/Q3ScBKzuncZviHlmRG jZQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7d3b8f470b3si1533529585a.609.2025.06.18.23.43.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Jun 2025 23:43:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS8xp-0002Ue-QB; Thu, 19 Jun 2025 02:41:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS8xn-0002Tv-QI; Thu, 19 Jun 2025 02:41:31 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS8xl-0001s1-Q5; Thu, 19 Jun 2025 02:41:31 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 19 Jun 2025 14:41:16 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 19 Jun 2025 14:41:16 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [RFC v5 1/4] hw/misc/aspeed_otp: Add ASPEED OTP memory device model Date: Thu, 19 Jun 2025 14:41:10 +0800 Message-ID: <20250619064115.4182202-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250619064115.4182202-1-kane_chen@aspeedtech.com> References: <20250619064115.4182202-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: y+1iUPpzHRMz From: Kane-Chen-AS Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage or boot-time configuration. The OTP memory can operate with either: - a file-backed backend via the 'drive' property, which allows persistent emulation of burned fuse states using -blockdev, or - an internal fallback buffer The OTP model provides a memory-like interface through a dedicated AddressSpace, allowing other device models (e.g., SBC) to issue transactions as if accessing a memory-mapped region. Actual data is maintained in a file-backed or internal buffer. Logging is included to assist with debugging and to indicate fallback behavior when no backend is provided. Signed-off-by: Kane-Chen-AS --- hw/misc/aspeed_otpmem.c | 117 ++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/aspeed_otpmem.h | 35 ++++++++++ 3 files changed, 153 insertions(+) create mode 100644 hw/misc/aspeed_otpmem.c create mode 100644 include/hw/misc/aspeed_otpmem.h diff --git a/hw/misc/aspeed_otpmem.c b/hw/misc/aspeed_otpmem.c new file mode 100644 index 0000000000..c5a67621c9 --- /dev/null +++ b/hw/misc/aspeed_otpmem.c @@ -0,0 +1,117 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "trace.h" +#include "system/block-backend-global-state.h" +#include "system/block-backend-io.h" +#include "hw/misc/aspeed_otpmem.h" + +static uint64_t aspeed_otpmem_read(void *opaque, hwaddr offset, unsigned size) +{ + AspeedOTPMemState *s = opaque; + uint64_t val = 0; + + memcpy(&val, s->storage + offset, size); + + return val; +} + +static void aspeed_otpmem_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + int ret; + AspeedOTPMemState *s = opaque; + + memcpy(s->storage + offset, &val, size); + if (s->blk) { + ret = blk_pwrite(s->blk, offset, size, &val, BDRV_REQ_FUA); + if (ret < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "blk_pwrite failed offset 0x%" HWADDR_PRIx + ", ret = %d\n", + offset, ret); + } + } +} + +static const MemoryRegionOps aspeed_otpmem_ops = { + .read = aspeed_otpmem_read, + .write = aspeed_otpmem_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 4, +}; + +static void aspeed_otpmem_realize(DeviceState *dev, Error **errp) +{ + AspeedOTPMemState *s = ASPEED_OTPMEM(dev); + const size_t size = OTPMEM_SIZE; + int i, num; + uint32_t *p; + + s->storage = blk_blockalign(s->blk, size); + if (!s->storage) { + error_setg(errp, "Failed to allocate OTP memory storage buffer"); + return; + } + + if (s->blk) { + uint64_t perm = BLK_PERM_CONSISTENT_READ | + (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); + if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) { + error_setg(errp, "Failed to set permission"); + return; + } + + if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) { + error_setg(errp, "Failed to read the initial flash content"); + return; + } + } else { + num = size / sizeof(uint32_t); + p = (uint32_t *)s->storage; + for (i = 0; i < num; i++) { + p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF; + } + qemu_log_mask(LOG_GUEST_ERROR, + "OTP image is not presented, use local buffer\n"); + } + + memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otpmem_ops, + s, "aspeed.otpmem", size); + address_space_init(&s->as, &s->mmio, NULL); +} + +static const Property aspeed_otpmem_properties[] = { + DEFINE_PROP_UINT64("size", AspeedOTPMemState, size, OTPMEM_SIZE), + DEFINE_PROP_DRIVE("drive", AspeedOTPMemState, blk), +}; + +static void aspeed_otpmem_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = aspeed_otpmem_realize; + device_class_set_props(dc, aspeed_otpmem_properties); +} + +static const TypeInfo aspeed_otpmem_info = { + .name = TYPE_ASPEED_OTPMEM, + .parent = TYPE_DEVICE, + .instance_size = sizeof(AspeedOTPMemState), + .class_init = aspeed_otpmem_class_init, +}; + +static void aspeed_otpmem_register_types(void) +{ + type_register_static(&aspeed_otpmem_info); +} + +type_init(aspeed_otpmem_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6d47de482c..ed1eaaa2ad 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_sbc.c', 'aspeed_sdmc.c', 'aspeed_xdma.c', + 'aspeed_otpmem.c', 'aspeed_peci.c', 'aspeed_sli.c')) diff --git a/include/hw/misc/aspeed_otpmem.h b/include/hw/misc/aspeed_otpmem.h new file mode 100644 index 0000000000..7f469d9fd7 --- /dev/null +++ b/include/hw/misc/aspeed_otpmem.h @@ -0,0 +1,35 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_OTPMMEM_H +#define ASPEED_OTPMMEM_H + +#include "system/memory.h" +#include "hw/block/block.h" +#include "system/memory.h" +#include "system/address-spaces.h" + +#define OTPMEM_SIZE 0x4000 +#define TYPE_ASPEED_OTPMEM "aspeed.otpmem" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPMemState, ASPEED_OTPMEM) + +typedef struct AspeedOTPMemState { + DeviceState parent_obj; + + BlockBackend *blk; + + uint64_t size; + + AddressSpace as; + + MemoryRegion mmio; + + uint8_t *storage; +} AspeedOTPMemState; + +#endif /* ASPEED_OTPMMEM_H */ -- 2.43.0