From: Shubhi Garg <shgarg@nvidia.com>
To: Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"Catalin Marinas" <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-rtc@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Shubhi Garg <shgarg@nvidia.com>
Subject: [PATCH v4 6/6] MAINTAINERS: Add NVIDIA VRS PSEQ driver entry
Date: Thu, 19 Jun 2025 08:44:27 +0000 [thread overview]
Message-ID: <20250619084427.3559207-7-shgarg@nvidia.com> (raw)
In-Reply-To: <20250619084427.3559207-1-shgarg@nvidia.com>
Add NVIDIA VRS (Voltage Regulator Specification) power sequencer driver
entry in MAINTAINERS.
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
---
v4:
- no changes
v3:
- fixed indentation
v2:
- this is a new patch in V2
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9165216d0cc0..11030db537ff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17846,6 +17846,15 @@ S: Maintained
F: drivers/video/fbdev/nvidia/
F: drivers/video/fbdev/riva/
+NVIDIA VRS POWER SEQUENCER
+M: Shubhi Garg <shgarg@nvidia.com>
+L: linux-tegra@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
+F: drivers/mfd/nvidia-vrs-pseq.c
+F: drivers/rtc/rtc-nvidia-vrs-pseq.c
+F: include/linux/mfd/nvidia-vrs-pseq.h
+
NVIDIA WMI EC BACKLIGHT DRIVER
M: Daniel Dadap <ddadap@nvidia.com>
L: platform-driver-x86@vger.kernel.org
--
2.43.0
prev parent reply other threads:[~2025-06-19 9:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 8:44 [PATCH v4 0/6] Add NVIDIA VRS PSEQ support Shubhi Garg
2025-06-19 8:44 ` [PATCH v4 1/6] dt-bindings: mfd: add NVIDIA VRS PSEQ Shubhi Garg
2025-06-22 11:36 ` Krzysztof Kozlowski
2025-06-19 8:44 ` [PATCH v4 2/6] arm64: tegra: Add device-tree node for NVVRS PSEQ Shubhi Garg
2025-06-19 8:44 ` [PATCH v4 3/6] mfd: nvvrs: add NVVRS PSEQ MFD driver Shubhi Garg
2025-06-25 11:29 ` Lee Jones
2025-06-19 8:44 ` [PATCH v4 4/6] rtc: nvvrs: add NVIDIA VRS PSEQ RTC device driver Shubhi Garg
2025-06-19 8:44 ` [PATCH v4 5/6] arm64: defconfig: enable NVIDIA VRS PSEQ Shubhi Garg
2025-06-19 8:44 ` Shubhi Garg [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250619084427.3559207-7-shgarg@nvidia.com \
--to=shgarg@nvidia.com \
--cc=alexandre.belloni@bootlin.com \
--cc=catalin.marinas@arm.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jonathanh@nvidia.com \
--cc=krzk+dt@kernel.org \
--cc=lee@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-rtc@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=robh@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.