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Mon, 23 Jun 2025 09:54:08 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:8947:973b:de:93b7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-453755e7d1dsm33747445e9.10.2025.06.23.09.54.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 09:54:08 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Atish Patra Subject: [PATCH 1/2] target/riscv: disable *stimecmp interrupts without *envcfg.STCE Date: Mon, 23 Jun 2025 18:53:28 +0200 Message-ID: <20250623165329.2759651-2-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623165329.2759651-1-rkrcmar@ventanamicro.com> References: <20250623165329.2759651-1-rkrcmar@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=rkrcmar@ventanamicro.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org The specification states that menvcfg.STCE=0 prevents both *stimecmp CSRs from having an effect on the pending interrupts. henvcfg.STCE=0 disables only vstimecmp. Make sure that when *envcfg.STCE is not set: * writing the *stimecmp CSRs doesn't modify the *ip CSRs, * and that the interrupt timer is disarmed. Call the *stimecmp CSR update functions when *envcfg.STCE is toggled, because the *ip CSRs need to immediately reflect the new behavior. Fixes: 43888c2f1823 ("target/riscv: Add stimecmp support") Signed-off-by: Radim Krčmář --- target/riscv/csr.c | 12 ++++++++++++ target/riscv/time_helper.c | 10 ++++++++++ 2 files changed, 22 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fb149721691d..43eae9bcf153 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3181,6 +3181,7 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE | MENVCFG_CDE; + typeof(env->menvcfg) old = env->menvcfg; if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | @@ -3208,6 +3209,11 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, } } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); + + if ((old ^ env->menvcfg) & MENVCFG_STCE) { + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); + } + return write_henvcfg(env, CSR_HENVCFG, env->henvcfg, ra); } @@ -3314,6 +3320,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + typeof(env->henvcfg) old = env->henvcfg; RISCVException ret; ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); @@ -3347,6 +3354,11 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, env->vsstatus &= ~MSTATUS_SDT; } + if ((old ^ env->henvcfg) & HENVCFG_STCE) { + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index bc0d9a0c4c35..8198a2d8d92d 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -49,6 +49,16 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, uint32_t timebase_freq = mtimer->timebase_freq; uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta; + /* + * *envcfg.STCE disables *stimecmp interrupts, but still allows higher + * privileges to write the *stimecmp CSRs. + */ + if (!get_field(env->menvcfg, MENVCFG_STCE) || + (timer_irq == MIP_VSTIP && !get_field(env->henvcfg, HENVCFG_STCE))) { + timer_del(timer); + return; + } + if (timecmp <= rtc_r) { /* * If we're setting an stimecmp value in the "past", -- 2.49.0