Re: [PATCH] dt-bindings: net: convert socfpga-dwmac.txt to DT schema

[Rob Herring <robh@kernel.org>]

On Fri, Jun 20, 2025 at 10:44:01PM -0500, Dinh Nguyen wrote:
> Convert the socfpga-dwmac.txt to yaml.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  .../bindings/net/altr,dwmac-socfpga.yaml      | 152 ++++++++++++++++++
>  .../devicetree/bindings/net/socfpga-dwmac.txt |  57 -------
>  2 files changed, 152 insertions(+), 57 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
>  delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml b/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
> new file mode 100644
> index 000000000000..fc088bd55178
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/altr,dwmac-socfpga.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel/Altera SoCFPGA DWMAC controller
> +
> +maintainers:
> +  - Dinh Nguyen <dinguyen@kernel.org>
> +

You'll need a custom 'select' to avoid matching on the common compatible 
strings.

> +properties:
> +  compatible:
> +    additionalItems: true
> +    maxItems: 3
> +    items:
> +      - enum:
> +          - altr,socfpga-stmmac
> +          - altr,socfpga-stmmac-a10-s10
> +    contains:
> +      enum:
> +        - snps,dwmac-3.74a
> +        - snps,dwmac-3.70a
> +        - snps,dwmac

Need to define the exact combinations of compatible strings which are 
valid.

> +
> +  reg:
> +    items:
> +      - description: Base DWMAC registers

Just 'maxItems: 1'

> +
> +  iommus:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clocks:
> +    minItems: 1
> +    items:
> +      - description: MAC host clock
> +      - description: MAC timer clock
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +    contains:
> +      enum:
> +        - stmmaceth
> +        - ptp_ref

'contains' passes if either of these strings is present and allows 
anything for the 2nd string. Use 'items' instead and define the exact 
order and entries.

> +
> +  resets:
> +    minItems: 1
> +    items:
> +      - description: GMAC stmmaceth reset
> +      - description: AHB reset
> +
> +  reset-names:
> +    oneOf:
> +      - items:
> +          - enum: [stmmaceth, ahb]

Drop this and add 'minItems: 1' below.

> +      - items:
> +          - const: stmmaceth
> +          - const: ahb
> +
> +  interrupts:
> +    items:
> +      - description: DWAC interrupt

typo.

> +
> +  interrupt-names:
> +    items:
> +      - const: macirq
> +
> +  mac-address: true

Drop

> +
> +  phy-mode:
> +    maxItems: 1
> +    items:
> +      enum:
> +        - rgmii
> +        - gmii
> +        - mii
> +
> +  tx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: DWMAC Tx fifo depth(Stratix10, Agilex)
> +
> +  rx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: DWMAC Rx fifo depth(Stratix10, Agilex)

Already defined in ethernet-controller.yaml. Drop unless you have 
additional constaints on them.

> +
> +  snps,multicast-filter-bins:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Number of multicast filter hash bins supported by this device
> +      instance

Already defined in snps,dwmac.yaml. Drop unless you have additional 
constaints on it.

> +
> +  altr,sysmgr-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to the sysmgr node
> +          - description: register offset that controls the SDMMC clock phase
> +          - description: register shift for the smplsel(drive in) setting
> +    description:
> +      Should be the phandle to the system manager node that
> +      encompasses the glue register, the register offset, and the register shift.
> +      On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
> +      on the Arria10/Stratix10/Agilex platforms, the register shift represents
> +      bit for each emac to enable/disable signals from the FPGA fabric to the
> +      EMAC modules.
> +
> +  altr,emac-splitter:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Should be the phandle to the emac splitter soft IP node if DWMAC
> +      controller is connected emac splitter.
> +
> +  altr,sgmii-to-sgmii-converter:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to the TSE SGMII converter.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - phy-mode
> +
> +allOf:
> +  - $ref: snps,dwmac.yaml#
> +
> +additionalProperties: false

unevaluatedProperties: false

> +
> +examples:
> +  - |
> +    soc {
> +        #address-cells = <1>;
> +        #size-cells = <1>;

Don't need this node.

> +
> +        gmac0: ethernet@ff700000 {
> +            compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
> +            altr,sysmgr-syscon = <&sysmgr 0x60 0>;
> +            reg = <0xff700000 0x2000>;
> +            interrupts = <0 115 4>;
> +            interrupt-names = "macirq";
> +            mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
> +            clocks = <&emac_0_clk>;
> +            clock-names = "stmmaceth";
> +            phy-mode = "rgmii";
> +            tx-fifo-depth = <16384>;
> +            rx-fifo-depth = <16384>;
> +       };
> +    };