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From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>, <christian.koenig@amd.com>,
	<sasundar@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 03/33] drm/amdgpu/sdma: allow caller to handle kernel rings in engine reset
Date: Thu, 26 Jun 2025 23:39:32 -0400	[thread overview]
Message-ID: <20250627034002.5590-4-alexander.deucher@amd.com> (raw)
In-Reply-To: <20250627034002.5590-1-alexander.deucher@amd.com>

Add a parameter to amdgpu_sdma_reset_engine() to let the
caller handle the kernel rings.  This allows the kernel
rings to back up their unprocessed state if the reset comes in
via the drm scheduler rather than KFD.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c      | 44 +++++++++++--------
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h      |  3 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c        |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c        |  2 +-
 .../drm/amd/amdkfd/kfd_device_queue_manager.c |  2 +-
 6 files changed, 32 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 56939bb1d1a95..8b8a04138711c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -545,10 +545,13 @@ static int amdgpu_sdma_soft_reset(struct amdgpu_device *adev, u32 instance_id)
  * amdgpu_sdma_reset_engine - Reset a specific SDMA engine
  * @adev: Pointer to the AMDGPU device
  * @instance_id: Logical ID of the SDMA engine instance to reset
+ * @caller_handles_kernel_queues: Skip kernel queue processing. Caller
+ * will handle it.
  *
  * Returns: 0 on success, or a negative error code on failure.
  */
-int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
+			     bool caller_handles_kernel_queues)
 {
 	int ret = 0;
 	struct amdgpu_sdma_instance *sdma_instance = &adev->sdma.instance[instance_id];
@@ -556,14 +559,17 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
 	struct amdgpu_ring *page_ring = &sdma_instance->page;
 
 	mutex_lock(&sdma_instance->engine_reset_mutex);
-	/* Stop the scheduler's work queue for the GFX and page rings if they are running.
-	* This ensures that no new tasks are submitted to the queues while
-	* the reset is in progress.
-	*/
-	drm_sched_wqueue_stop(&gfx_ring->sched);
 
-	if (adev->sdma.has_page_queue)
-		drm_sched_wqueue_stop(&page_ring->sched);
+	if (!caller_handles_kernel_queues) {
+		/* Stop the scheduler's work queue for the GFX and page rings if they are running.
+		 * This ensures that no new tasks are submitted to the queues while
+		 * the reset is in progress.
+		 */
+		drm_sched_wqueue_stop(&gfx_ring->sched);
+
+		if (adev->sdma.has_page_queue)
+			drm_sched_wqueue_stop(&page_ring->sched);
+	}
 
 	if (sdma_instance->funcs->stop_kernel_queue) {
 		sdma_instance->funcs->stop_kernel_queue(gfx_ring);
@@ -585,16 +591,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
 	}
 
 exit:
-	/* Restart the scheduler's work queue for the GFX and page rings
-	 * if they were stopped by this function. This allows new tasks
-	 * to be submitted to the queues after the reset is complete.
-	 */
-	if (!ret) {
-		amdgpu_fence_driver_force_completion(gfx_ring);
-		drm_sched_wqueue_start(&gfx_ring->sched);
-		if (adev->sdma.has_page_queue) {
-			amdgpu_fence_driver_force_completion(page_ring);
-			drm_sched_wqueue_start(&page_ring->sched);
+	if (!caller_handles_kernel_queues) {
+		/* Restart the scheduler's work queue for the GFX and page rings
+		 * if they were stopped by this function. This allows new tasks
+		 * to be submitted to the queues after the reset is complete.
+		 */
+		if (!ret) {
+			amdgpu_fence_driver_force_completion(gfx_ring);
+			drm_sched_wqueue_start(&gfx_ring->sched);
+			if (adev->sdma.has_page_queue) {
+				amdgpu_fence_driver_force_completion(page_ring);
+				drm_sched_wqueue_start(&page_ring->sched);
+			}
 		}
 	}
 	mutex_unlock(&sdma_instance->engine_reset_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5f8951bbb6f4..34311f32be4c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -172,7 +172,8 @@ struct amdgpu_buffer_funcs {
 				 uint32_t byte_count);
 };
 
-int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id);
+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
+			     bool caller_handles_kernel_queues);
 
 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b), (t))
 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 572d105420ec3..c0c418aa2c299 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1668,7 +1668,7 @@ static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,
 		return -EOPNOTSUPP;
 
 	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, id);
+	r = amdgpu_sdma_reset_engine(adev, id, false);
 	amdgpu_amdkfd_resume(adev, true);
 	return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index ed1706da7deec..5a1098bdd8256 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1548,7 +1548,7 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring,
 	int r;
 
 	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, inst_id);
+	r = amdgpu_sdma_reset_engine(adev, inst_id, false);
 	amdgpu_amdkfd_resume(adev, true);
 
 	return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index b87a4b44fa939..6843c2c3d71f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1461,7 +1461,7 @@ static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring,
 	int r;
 
 	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, inst_id);
+	r = amdgpu_sdma_reset_engine(adev, inst_id, false);
 	amdgpu_amdkfd_resume(adev, true);
 
 	return r;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 76359c6a3f3a4..f0d19f6ed9ba8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -2312,7 +2312,7 @@ static int reset_hung_queues_sdma(struct device_queue_manager *dqm)
 				continue;
 
 			/* Reset engine and check. */
-			if (amdgpu_sdma_reset_engine(dqm->dev->adev, i) ||
+			if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) ||
 			    dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j) ||
 			    !set_sdma_queue_as_reset(dqm, doorbell_off)) {
 				r = -ENOTRECOVERABLE;
-- 
2.50.0


  parent reply	other threads:[~2025-06-27  3:40 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-27  3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
2025-06-27  3:39 ` [PATCH 01/33] drm/amdgpu/gfx10: fix KGQ reset sequence Alex Deucher
2025-06-30  8:37   ` Christian König
2025-06-27  3:39 ` [PATCH 02/33] drm/amdgpu/sdma: consolidate engine reset handling Alex Deucher
2025-06-30  8:40   ` Christian König
2025-06-30 13:47     ` Alex Deucher
2025-06-27  3:39 ` Alex Deucher [this message]
2025-06-27  3:39 ` [PATCH 04/33] drm/amdgpu/sdma5: clean up resume code Alex Deucher
2025-06-30  8:52   ` Christian König
2025-06-27  3:39 ` [PATCH 05/33] drm/amdgpu/sdma5.2: " Alex Deucher
2025-06-30  8:53   ` Christian König
2025-06-27  3:39 ` [PATCH 06/33] drm/amdgpu/sdma6: " Alex Deucher
2025-06-30  8:55   ` Christian König
2025-06-27  3:39 ` [PATCH 07/33] drm/amdgpu/sdma7: " Alex Deucher
2025-06-30  8:56   ` Christian König
2025-06-27  3:39 ` [PATCH 08/33] drm/amdgpu: track ring state associated with a fence Alex Deucher
2025-06-27  3:39 ` [PATCH 09/33] drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset Alex Deucher
2025-06-27  3:39 ` [PATCH 10/33] drm/amdgpu/gfx9.4.3: " Alex Deucher
2025-06-27  3:39 ` [PATCH 11/33] drm/amdgpu/gfx10: re-emit unprocessed state on ring reset Alex Deucher
2025-06-27  3:39 ` [PATCH 12/33] drm/amdgpu/gfx11: " Alex Deucher
2025-06-27  3:39 ` [PATCH 13/33] drm/amdgpu/gfx12: " Alex Deucher
2025-06-27  3:39 ` [PATCH 14/33] drm/amdgpu/sdma5: " Alex Deucher
2025-06-27  3:39 ` [PATCH 15/33] drm/amdgpu/sdma5.2: " Alex Deucher
2025-06-27  3:39 ` [PATCH 16/33] drm/amdgpu/sdma6: " Alex Deucher
2025-06-27  3:39 ` [PATCH 17/33] drm/amdgpu/sdma7: " Alex Deucher
2025-06-27  3:39 ` [PATCH 18/33] drm/amdgpu/jpeg2: " Alex Deucher
2025-06-27  3:39 ` [PATCH 19/33] drm/amdgpu/jpeg2.5: " Alex Deucher
2025-06-27  3:39 ` [PATCH 20/33] drm/amdgpu/jpeg3: " Alex Deucher
2025-06-27  3:39 ` [PATCH 21/33] drm/amdgpu/jpeg4: " Alex Deucher
2025-06-27  3:39 ` [PATCH 22/33] drm/amdgpu/jpeg4.0.3: " Alex Deucher
2025-06-27  3:39 ` [PATCH 23/33] drm/amdgpu/jpeg4.0.5: add queue reset Alex Deucher
2025-06-27  3:39 ` [PATCH 24/33] drm/amdgpu/jpeg5: " Alex Deucher
2025-06-27  3:39 ` [PATCH 25/33] drm/amdgpu/jpeg5.0.1: re-emit unprocessed state on ring reset Alex Deucher
2025-06-27  3:39 ` [PATCH 26/33] drm/amdgpu/vcn4: " Alex Deucher
2025-06-27  3:39 ` [PATCH 27/33] drm/amdgpu/vcn4.0.3: " Alex Deucher
2025-06-27  3:39 ` [PATCH 28/33] drm/amdgpu/vcn4.0.5: " Alex Deucher
2025-06-27  3:39 ` [PATCH 29/33] drm/amdgpu/vcn5: " Alex Deucher
2025-06-27  3:39 ` [PATCH 30/33] drm/amdgpu/vcn: add a helper framework for engine resets Alex Deucher
2025-06-27  3:40 ` [PATCH 31/33] drm/amdgpu/vcn2: implement ring reset Alex Deucher
2025-06-27  3:40 ` [PATCH 32/33] drm/amdgpu/vcn2.5: " Alex Deucher
2025-06-27  3:40 ` [PATCH 33/33] drm/amdgpu/vcn3: " Alex Deucher
2025-07-01 15:25 ` [PATCH V12 00/33] Reset improvements Krzysztof Łopatowski
2025-07-01 15:30   ` Alex Deucher

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