From: Jason Gunthorpe <jgg@nvidia.com>
To: Easwar Hariharan <eahariha@linux.microsoft.com>
Cc: Joerg Roedel <joro@8bytes.org>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Vasant Hegde <vasant.hegde@amd.com>,
Jerry Snitselaar <jsnitsel@redhat.com>,
"open list:AMD IOMMU (AMD-VI)" <iommu@lists.linux.dev>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order
Date: Fri, 4 Jul 2025 09:51:51 -0300 [thread overview]
Message-ID: <20250704125151.GL1209783@nvidia.com> (raw)
In-Reply-To: <20250703155433.6221-1-eahariha@linux.microsoft.com>
On Thu, Jul 03, 2025 at 08:54:33AM -0700, Easwar Hariharan wrote:
> Per the PCIe spec, behavior of the PASID capability is undefined if the
> value of the PASID Enable bit changes while the Enable bit of the
> function's ATS control register is Set. Unfortunately,
> pdev_enable_caps() does exactly that by ordering enabling ATS for the
> device before enabling PASID.
>
> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Cc: Vasant Hegde <vasant.hegde@amd.com>
> Cc: Jason Gunthorpe <jgg@nvidia.com>
> Cc: Jerry Snitselaar <jsnitsel@redhat.com>
> Fixes: eda8c2860ab679 ("iommu/amd: Enable device ATS/PASID/PRI capabilities independently")
> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
> ---
> drivers/iommu/amd/iommu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
The other two drivers look like they do it Ok.
Jason
next prev parent reply other threads:[~2025-07-04 12:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-03 15:54 [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order Easwar Hariharan
2025-07-04 12:51 ` Jason Gunthorpe [this message]
2025-07-05 4:31 ` Vasant Hegde
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