From: Stefan Hajnoczi <stefanha@redhat.com>
To: alistair23@gmail.com
Cc: qemu-devel@nongnu.org, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/40] riscv-to-apply queue
Date: Fri, 4 Jul 2025 13:50:04 -0400 [thread overview]
Message-ID: <20250704175004.GA95199@fedora> (raw)
In-Reply-To: <20250704111207.591994-1-alistair.francis@wdc.com>
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes.
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next prev parent reply other threads:[~2025-07-04 17:52 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-04 11:11 [PULL 00/40] riscv-to-apply queue alistair23
2025-07-04 11:11 ` [PULL 01/40] target/riscv: Add the checking into stimecmp write function alistair23
2025-07-04 11:11 ` [PULL 02/40] hw/intc: riscv_aclint: Fix mtime write for sstc extension alistair23
2025-07-04 11:11 ` [PULL 03/40] target/riscv: Fix VSTIP bit in " alistair23
2025-07-04 11:11 ` [PULL 04/40] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed alistair23
2025-07-04 11:11 ` [PULL 05/40] target/riscv/cpu.c: fix zama16b order in isa_edata_arr[] alistair23
2025-07-04 11:11 ` [PULL 06/40] target/riscv/tcg: restrict satp_mode changes in cpu_set_profile alistair23
2025-07-04 11:11 ` [PULL 07/40] target/riscv/tcg: decouple profile enablement from user prop alistair23
2025-07-04 11:11 ` [PULL 08/40] target/riscv: add profile->present flag alistair23
2025-07-04 11:11 ` [PULL 09/40] target/riscv: Extend PMP region up to 64 alistair23
2025-07-04 11:11 ` [PULL 10/40] target/riscv: remove capital 'Z' CPU properties alistair23
2025-07-04 11:11 ` [PULL 11/40] target/riscv/cpu.c: add 'sdtrig' in riscv,isa alistair23
2025-07-04 11:11 ` [PULL 12/40] target/riscv/cpu.c: add 'ssstrict' to riscv, isa alistair23
2025-07-04 11:11 ` [PULL 13/40] target/riscv/cpu.c: do better with 'named features' doc alistair23
2025-07-04 11:11 ` [PULL 14/40] target/riscv: support atomic instruction fetch (Ziccif) alistair23
2025-07-04 11:11 ` [PULL 15/40] target/riscv/kvm: add max_satp_mode from host cpu alistair23
2025-07-04 11:11 ` [PULL 16/40] target/riscv: Make PMP region count configurable alistair23
2025-07-04 11:11 ` [PULL 17/40] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register alistair23
2025-07-04 11:11 ` [PULL 18/40] target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE alistair23
2025-07-04 11:11 ` [PULL 19/40] target/riscv: Fix fcvt.s.bf16 NaN box checking alistair23
2025-07-04 11:11 ` [PULL 20/40] hw/char: sifive_uart: Avoid infinite delay of async xmit function alistair23
2025-07-04 11:11 ` [PULL 21/40] hw/riscv/virt: Fix clint base address type alistair23
2025-07-04 11:11 ` [PULL 22/40] hw/riscv/virt: Use setprop_sized_cells for clint alistair23
2025-07-04 11:11 ` [PULL 23/40] hw/riscv/virt: Use setprop_sized_cells for memory alistair23
2025-07-04 11:11 ` [PULL 24/40] hw/riscv/virt: Use setprop_sized_cells for aplic alistair23
2025-07-04 11:11 ` [PULL 25/40] hw/riscv/virt: Use setprop_sized_cells for aclint alistair23
2025-07-04 11:11 ` [PULL 26/40] hw/riscv/virt: Use setprop_sized_cells for plic alistair23
2025-07-04 11:11 ` [PULL 27/40] hw/riscv/virt: Use setprop_sized_cells for virtio alistair23
2025-07-04 11:11 ` [PULL 28/40] hw/riscv/virt: Use setprop_sized_cells for reset alistair23
2025-07-04 11:11 ` [PULL 29/40] hw/riscv/virt: Use setprop_sized_cells for uart alistair23
2025-07-04 11:11 ` [PULL 30/40] hw/riscv/virt: Use setprop_sized_cells for rtc alistair23
2025-07-04 11:11 ` [PULL 31/40] hw/riscv/virt: Use setprop_sized_cells for iommu alistair23
2025-07-04 11:11 ` [PULL 32/40] hw/riscv/virt: Use setprop_sized_cells for pcie alistair23
2025-07-04 11:12 ` [PULL 33/40] target/riscv: Add BOSC's Xiangshan Kunminghu CPU alistair23
2025-07-04 11:12 ` [PULL 34/40] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype alistair23
2025-07-04 11:12 ` [PULL 35/40] target/riscv: rvv: Fix missing exit TB flow for ldff_trans alistair23
2025-07-04 11:12 ` [PULL 36/40] migration: Fix migration failure when aia is configured as aplic-imsic alistair23
2025-07-04 11:12 ` [PULL 37/40] target/riscv: Fix MEPC/SEPC bit masking for IALIGN alistair23
2025-07-04 11:12 ` [PULL 38/40] tests/tcg/riscv64: Add test for MEPC bit masking alistair23
2025-07-04 11:12 ` [PULL 39/40] target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction alistair23
2025-07-04 11:12 ` [PULL 40/40] target: riscv: Add Svrsw60t59b extension support alistair23
2025-07-04 17:50 ` Stefan Hajnoczi [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-02-11 23:59 [PULL 00/40] riscv-to-apply queue Alistair Francis
2022-02-15 11:39 ` Peter Maydell
2022-02-16 6:28 ` Alistair Francis
2022-02-16 6:45 ` Anup Patel
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