From: Simon Horman <horms@kernel.org>
To: Suraj Gupta <suraj.gupta2@amd.com>
Cc: andrew+netdev@lunn.ch, davem@davemloft.net, kuba@kernel.org,
pabeni@redhat.com, michal.simek@amd.com, vkoul@kernel.org,
radhey.shyam.pandey@amd.com, netdev@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
harini.katakam@amd.com
Subject: Re: [PATCH V2 2/4] dmaengine: xilinx_dma: Fix irq handler and start transfer path for AXI DMA
Date: Thu, 10 Jul 2025 12:26:50 +0100 [thread overview]
Message-ID: <20250710112650.GS721198@horms.kernel.org> (raw)
In-Reply-To: <20250710101229.804183-3-suraj.gupta2@amd.com>
On Thu, Jul 10, 2025 at 03:42:27PM +0530, Suraj Gupta wrote:
> AXI DMA driver incorrectly assumes complete transfer completion upon
> IRQ reception, particularly problematic when IRQ coalescing is active.
> Updating the tail pointer dynamically fixes it.
> Remove existing idle state validation in the beginning of
> xilinx_dma_start_transfer() as it blocks valid transfer initiation on
> busy channels with queued descriptors.
> Additionally, refactor xilinx_dma_start_transfer() to consolidate coalesce
> and delay configurations while conditionally starting channels
> only when idle.
>
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> Fixes: Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine")
Hi,
This is not a proper review.
And there is probably no need to repost just becuse of it.
But:
s/Fixes: Fixes: /Fixes: /
...
next prev parent reply other threads:[~2025-07-10 11:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 10:12 [PATCH V2 0/4] Add ethtool support to configure irq coalescing count and delay Suraj Gupta
2025-07-10 10:12 ` [PATCH V2 1/4] dmaengine: Add support to configure and read IRQ coalescing parameters Suraj Gupta
2025-07-23 7:30 ` Vinod Koul
2025-07-23 11:49 ` Gupta, Suraj
2025-08-25 6:17 ` Gupta, Suraj
2025-08-25 11:30 ` Vinod Koul
2025-07-10 10:12 ` [PATCH V2 2/4] dmaengine: xilinx_dma: Fix irq handler and start transfer path for AXI DMA Suraj Gupta
2025-07-10 11:26 ` Simon Horman [this message]
2025-07-11 5:32 ` Folker Schwesinger
2025-07-11 16:26 ` Subbaraya Sundeep
2025-07-11 20:13 ` Gupta, Suraj
2025-07-12 5:36 ` Subbaraya Sundeep
2025-07-15 11:05 ` Pandey, Radhey Shyam
2025-07-10 10:12 ` [PATCH V2 3/4] dmaengine: xilinx_dma: Add support to configure/report coalesce parameters from/to client using " Suraj Gupta
2025-07-10 10:12 ` [PATCH V2 4/4] net: xilinx: axienet: Add ethtool support to configure/report irq coalescing parameters in DMAengine flow Suraj Gupta
2025-07-11 16:33 ` Subbaraya Sundeep
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