[PATCH 2/2] arm64/dts/blaize: Enable Ethernet on CB2 board

[Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>]

Use the Synopsys gigabit Ethernet controller on the Blaize BLZP1600
SoC to provide Ethernet connectivity using the TI DP83867 PHY which is
available on the CB2 board via an RJ45 connector.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
index fb5415eb347a028fc65090027a4c4fc89c8280f5..cbe8f0930ad3741b0e770dd7d494931e3b939815 100644
--- a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "blaize-blzp1600-som.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
 
 / {
 	model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
@@ -14,6 +15,7 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet = &gmac;
 	};
 
 	chosen {
@@ -117,3 +119,23 @@ &gpio0 {
 			  "BOARD_ID_1",		/* GPIO_30 */
 			  "BOARD_ID_2";		/* GPIO_31 */
 };
+
+&gmac {
+	status = "okay";
+	snps,reset-delays-us = <0 10000 50000>;
+	snps,reset-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_6_B_NIB>;
+		};
+	};
+};

-- 
2.43.0