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Thu, 17 Jul 2025 15:22:09 +0800 (CST) From: Peter Chen To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, jassisinghbrar@gmail.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, maz@kernel.org, sudeep.holla@arm.com, kajetan.puchalski@arm.com, eballetb@redhat.com, Guomin Chen , Krzysztof Kozlowski , Peter Chen , Lihua Liu Subject: [PATCH v10 4/9] dt-bindings: mailbox: add cix,sky1-mbox Date: Thu, 17 Jul 2025 15:22:04 +0800 Message-Id: <20250717072209.176807-5-peter.chen@cixtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250717072209.176807-1-peter.chen@cixtech.com> References: <20250717072209.176807-1-peter.chen@cixtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CD:EE_|TYQPR06MB8119:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 8e070abb-88b1-4997-c4b9-08ddc502a517 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2025 07:22:10.5275 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e070abb-88b1-4997-c4b9-08ddc502a517 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CD.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYQPR06MB8119 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250717_002222_902686_D9BFC25E X-CRM114-Status: GOOD ( 14.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Guomin Chen Add a dt-binding for the Cixtech Mailbox Controller. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Chen Signed-off-by: Guomin Chen Signed-off-by: Lihua Liu Signed-off-by: Peter Chen --- Changes for v10: - Update the description of the Sky1 SoC use case. Changes for v7: - Add Krzysztof Kozlowski Reviewed-by tag - Add my Sob tag Changes for v3: - Replace the direction attribute of the mailbox with the strings "rx" and "tx" .../bindings/mailbox/cix,sky1-mbox.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml b/Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml new file mode 100644 index 000000000000..66d75b7bc8c8 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cixtech mailbox controller + +maintainers: + - Guomin Chen + +description: + The Cixtech mailbox controller, used in the Cixtech Sky1 SoC, + is used for message transmission between multiple processors + within the SoC, such as the AP, PM, audio DSP, SensorHub MCU, + and others + + Each Cixtech mailbox controller is unidirectional, so they are + typically used in pairs-one for receiving and one for transmitting. + + Each Cixtech mailbox supports 11 channels with different transmission modes + channel 0-7 - Fast channel with 32bit transmit register and IRQ support + channel 8 - Doorbell mode,using the mailbox as an interrupt-generating + mechanism. + channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support + channel 10 - Reg based channel with 32*32bit transmit register and + Doorbell+transmit acknowledgment IRQ support + + In the CIX Sky1 SoC use case, there are 4 pairs of mailbox controllers + AP <--> PM - using Doorbell transfer mode + AP <--> SE - using REG transfer mode + AP <--> DSP - using FIFO transfer mode + AP <--> SensorHub - using FIFO transfer mode + +properties: + compatible: + const: cix,sky1-mbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + + cix,mbox-dir: + $ref: /schemas/types.yaml#/definitions/string + description: Direction of the mailbox relative to the AP + enum: [tx, rx] + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + - cix,mbox-dir + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + mbox_ap2pm: mailbox@30000000 { + compatible = "cix,sky1-mbox"; + reg = <0 0x30000000 0 0x10000>; + interrupts = ; + #mbox-cells = <1>; + cix,mbox-dir = "tx"; + }; + }; -- 2.25.1