Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers

[Rob Herring <robh@kernel.org>]

On Wed, Jul 30, 2025 at 12:56:35PM +0200, Laura Nao wrote:
> Add new binding documentation for system clocks, functional clocks and
> PEXTP0/1 and UFS reset controllers on MediaTek MT8196.
> 
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Laura Nao <laura.nao@collabora.com>
> ---
>  .../bindings/clock/mediatek,mt8196-clock.yaml |  86 ++
>  .../clock/mediatek,mt8196-sys-clock.yaml      |  81 ++
>  .../dt-bindings/clock/mediatek,mt8196-clock.h | 802 ++++++++++++++++++
>  .../reset/mediatek,mt8196-resets.h            |  26 +
>  4 files changed, 995 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
>  create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
>  create mode 100644 include/dt-bindings/clock/mediatek,mt8196-clock.h
>  create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
> new file mode 100644
> index 000000000000..03ee0dff464b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
> @@ -0,0 +1,86 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Functional Clock Controller for MT8196
> +
> +maintainers:
> +  - Guangjie Song <guangjie.song@mediatek.com>
> +  - Laura Nao <laura.nao@collabora.com>
> +
> +description: |
> +  The clock architecture in MediaTek SoCs is structured like below:
> +  PLLs -->
> +          dividers -->
> +                      muxes
> +                           -->
> +                              clock gate
> +
> +  The device nodes provide clock gate control in different IP blocks.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt8196-imp-iic-wrap-c
> +          - mediatek,mt8196-imp-iic-wrap-e
> +          - mediatek,mt8196-imp-iic-wrap-n
> +          - mediatek,mt8196-imp-iic-wrap-w
> +          - mediatek,mt8196-mdpsys0
> +          - mediatek,mt8196-mdpsys1
> +          - mediatek,mt8196-pericfg-ao
> +          - mediatek,mt8196-pextp0cfg-ao
> +          - mediatek,mt8196-pextp1cfg-ao
> +          - mediatek,mt8196-ufscfg-ao
> +          - mediatek,mt8196-vencsys
> +          - mediatek,mt8196-vencsys-c1
> +          - mediatek,mt8196-vencsys-c2
> +          - mediatek,mt8196-vdecsys
> +          - mediatek,mt8196-vdecsys-soc
> +          - mediatek,mt8196-vdisp-ao
> +      - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#reset-cells':
> +    const: 1
> +    description:
> +      Reset lines for PEXTP0/1 and UFS blocks.
> +
> +  mediatek,hardware-voter:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
> +      MCU manages clock and power domain control across the AP and other
> +      remote processors. By aggregating their votes, it ensures clocks are
> +      safely enabled/disabled and power domains are active before register
> +      access.

I thought this was going away based on v2 discussion?

Rob