[openeuler:openEuler-1.0-LTS 1743/1743] arch/x86/kernel/cpu/cacheinfo.c:685:6: warning: no previous prototype for 'cacheinfo_hygon_init_llc_id'

[kernel test robot <lkp@intel.com>]

tree:   https://gitee.com/openeuler/kernel.git openEuler-1.0-LTS
head:   5c1061eccd6b1d6c12741278240a2b93ff91a0a8
commit: 1a0525a3d6d3c9c8effb3ae49581ef8ef99d8b26 [1743/1743] x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
config: x86_64-buildonly-randconfig-2004-20250802 (https://download.01.org/0day-ci/archive/20250805/202508050522.5Dp2I0DP-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250805/202508050522.5Dp2I0DP-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508050522.5Dp2I0DP-lkp@intel.com/

All warnings (new ones prefixed by >>):

   arch/x86/kernel/cpu/cacheinfo.c:647:6: warning: no previous prototype for 'cacheinfo_amd_init_llc_id' [-Wmissing-prototypes]
     647 | void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/x86/kernel/cpu/cacheinfo.c:685:6: warning: no previous prototype for 'cacheinfo_hygon_init_llc_id' [-Wmissing-prototypes]
     685 | void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~
   arch/x86/kernel/cpu/cacheinfo.c: In function 'amd_cpuid4':
   arch/x86/kernel/cpu/cacheinfo.c:249:20: warning: this statement may fall through [-Wimplicit-fallthrough=]
     249 |                 l1 = &l1i;
         |                 ~~~^~~~~~
   arch/x86/kernel/cpu/cacheinfo.c:250:9: note: here
     250 |         case 0:
         |         ^~~~


vim +/cacheinfo_hygon_init_llc_id +685 arch/x86/kernel/cpu/cacheinfo.c

   684	
 > 685	void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
   686	{
   687		/*
   688		 * We may have multiple LLCs if L3 caches exist, so check if we
   689		 * have an L3 cache by looking at the L3 cache CPUID leaf.
   690		 */
   691		if (!cpuid_edx(0x80000006))
   692			return;
   693	
   694		/*
   695		 * LLC is at the core complex level.
   696		 * Core complex ID is ApicId[3] for these processors.
   697		 */
   698		per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
   699	}
   700	

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