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The issue in the driver is due to overlooking a change on LNL+ in the way the PHY ready flag and pin assignment is set/cleared in the PHY registers by the HW/FW wrt. how this works on all the earlier (ICL-MTL) TypeC platforms. The first 5 patches fix the issue, the rest refactor the PHY's max lane count and pin assignment query functions, sanitizing the code, removing duplications and validating the register values read out from the HW. Reported-by: Charlton Lin Tested-by: Khaled Almahallawy Imre Deak (19): drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink drm/i915/icl+/tc: Cache the max lane count value drm/i915/lnl+/tc: Fix max lane count HW readout drm/i915/lnl+/tc: Use the cached max lane count value drm/i915/icl+/tc: Convert AUX powered WARN to a debug message drm/i915/tc: Use the cached max lane count value drm/i915/tc: Move getting the power domain before reading DFLEX registers drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUS drm/i915/tc: Add an enum for the TypeC pin assignment drm/i915/tc: Pass pin assignment value around using the pin assignment enum drm/i915/tc: Handle pin assignment NONE on all platforms drm/i915/tc: Validate the pin assignment on all platforms drm/i915/tc: Unify the way to get the pin assignment on all platforms drm/i915/tc: Unify the way to get the max lane count value on MTL+ drm/i915/tc: Handle non-TC encoders when getting the pin assignment drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers dmc/i915/tc: Report pin assignment NONE in TBT-alt mode drm/i915/tc: Cache the pin assignment value drm/i915/tc: Debug print the pin assignment and max lane count drivers/gpu/drm/i915/display/intel_ddi.c | 19 +- .../gpu/drm/i915/display/intel_display_regs.h | 2 + drivers/gpu/drm/i915/display/intel_tc.c | 217 ++++++++++++------ drivers/gpu/drm/i915/display/intel_tc.h | 72 +++++- 4 files changed, 225 insertions(+), 85 deletions(-) -- 2.49.1