From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: peng guo <engguopeng@buaa.edu.cn>
Cc: <mst@redhat.com>, <marcel.apfelbaum@gmail.com>,
<pbonzini@redhat.com>, <richard.henderson@linaro.org>,
<eduardo@habkost.net>, <qemu-devel@nongnu.org>,
<wyguopeng@163.com>
Subject: Re: [PATCH v3] hw/i386/pc: Avoid overlap between CXL window and PCI 64bit BARs in QEMU
Date: Wed, 6 Aug 2025 11:41:20 +0100 [thread overview]
Message-ID: <20250806114120.00000d27@huawei.com> (raw)
In-Reply-To: <20250805142300.15226-1-engguopeng@buaa.edu.cn>
On Tue, 5 Aug 2025 22:23:00 +0800
peng guo <engguopeng@buaa.edu.cn> wrote:
> When using a CXL Type 3 device together with a virtio 9p device in QEMU on a
> physical server, the 9p device fails to initialize properly. The kernel reports
> the following error:
>
> virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1
> 9pnet_virtio virtio0: probe with driver 9pnet_virtio failed with error -22
>
> Further investigation revealed that the 64-bit BAR space assigned to the 9pnet
> device was overlapped by the memory window allocated for the CXL devices. As a
> result, the kernel could not correctly access the BAR region, causing the
> virtio device to malfunction.
>
> An excerpt from /proc/iomem shows:
>
> 480010000-cffffffff : CXL Window 0
> 480010000-4bfffffff : PCI Bus 0000:00
> 4c0000000-4c01fffff : PCI Bus 0000:0c
> 4c0000000-4c01fffff : PCI Bus 0000:0d
> 4c0200000-cffffffff : PCI Bus 0000:00
> 4c0200000-4c0203fff : 0000:00:03.0
> 4c0200000-4c0203fff : virtio-pci-modern
>
> To address this issue, this patch adds the reserved memory end calculation
> for cxl devices to reserve sufficient address space and ensure that CXL memory
> windows are allocated beyond all PCI 64-bit BARs. This prevents overlap with
> 64-bit BARs regions such as those used by virtio or other pcie devices,
> resolving the conflict.
>
> QEMU Build Configuration:
>
> ./configure --prefix=/home/work/qemu_master/build/ \
> --target-list=x86_64-softmmu \
> --enable-kvm \
> --enable-virtfs
>
> QEMU Boot Command:
>
> sudo /home/work/qemu_master/qemu/build/qemu-system-x86_64 \
> -nographic -machine q35,cxl=on -enable-kvm -m 16G -smp 8 \
> -hda /home/work/gp_qemu/rootfs.img \
> -virtfs local,path=/home/work/gp_qemu/share,mount_tag=host0,security_model=passthrough,id=host0 \
> -kernel /home/work/linux_output/arch/x86/boot/bzImage \
> --append "console=ttyS0 crashkernel=256M root=/dev/sda rootfstype=ext4 rw loglevel=8" \
> -object memory-backend-ram,id=vmem0,share=on,size=4096M \
> -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
> -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \
> -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0,sn=0x123456789 \
> -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G
>
> Fixes: 03b39fcf64bc ("hw/cxl: Make the CXL fixed memory window setup a machine parameter")
> Signed-off-by: peng guo <engguopeng@buaa.edu.cn>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Thanks for fixing this up!
Jonathan
prev parent reply other threads:[~2025-08-06 10:52 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-05 14:23 [PATCH v3] hw/i386/pc: Avoid overlap between CXL window and PCI 64bit BARs in QEMU peng guo via
2025-08-06 10:41 ` Jonathan Cameron via [this message]
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