From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 901F2C87FD3 for ; Wed, 6 Aug 2025 22:24:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3DA8F10E7D3; Wed, 6 Aug 2025 22:24:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DAH3jXXE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38E8F10E156 for ; Wed, 6 Aug 2025 22:24:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754519047; x=1786055047; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jaAbTulb1p0dMDUSpRmhww9CC9ZvBkJkxAhlaafZVwM=; b=DAH3jXXEka0IWcroXbndFNKlMwmMsRGtLDtNs51UpxbDNAIJDWjYUCJK jYee2C3He/HJngVhJI58O7+mLlHAF7z7fl5TMBDVbsHbhDTtSM237uEtG FBA4E/tVbhtNdQA1OUbKxYdZdlusAbYqq/Ng3w/jlodiKcJPeCSOLjtKc jxAZW3Vxs00INJBND+7Cnx6I0vbjZCMGnrf2vXG+VUjPkxxQIzK0oyTqO d1PYP5UXiCEXMkqDGgAkWLB2cnXpN3whbt5Lq971jMMpAy0n7LXhg+o+I hG4/TPtGzTODZQ8jU2wfmuaj4wJnk81jMx3kvmn0GRMsBsUGHwdlsS/Kn g==; X-CSE-ConnectionGUID: Pt0yClSQRWuAQIDLmUrGMA== X-CSE-MsgGUID: 9ydqWjdmTxKxB8gWMn9kkg== X-IronPort-AV: E=McAfee;i="6800,10657,11514"; a="56928151" X-IronPort-AV: E=Sophos;i="6.17,271,1747724400"; d="scan'208";a="56928151" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 15:24:07 -0700 X-CSE-ConnectionGUID: /nEh3OMORP2q2d3jIfGEkQ== X-CSE-MsgGUID: 2O81F5H7RCeeMXGtBfS3QA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,271,1747724400"; d="scan'208";a="188560825" Received: from dut136arlu.fm.intel.com ([10.105.23.73]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 15:24:07 -0700 From: stuartsummers To: Cc: matthew.brost@intel.com, farah.kassabri@intel.com, intel-xe@lists.freedesktop.org, Stuart Summers Subject: [PATCH 3/8] drm/xe: Add xe_tlb_inval structure Date: Wed, 6 Aug 2025 22:23:59 +0000 Message-Id: <20250806222404.30333-4-stuart.summers@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250806222404.30333-1-stuart.summers@intel.com> References: <20250806222404.30333-1-stuart.summers@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" From: Matthew Brost Extract TLB invalidation state into a structure to decouple TLB invalidations from the GT, allowing the structure to be embedded anywhere in the driver. Signed-off-by: Matthew Brost Signed-off-by: Stuart Summers Reviewed-by: Stuart Summers --- drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h | 32 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_gt_types.h | 31 ++------------------- 2 files changed, 34 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h index 919430359103..8b37d0b8f545 100644 --- a/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h +++ b/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h @@ -6,10 +6,42 @@ #ifndef _XE_GT_TLB_INVAL_TYPES_H_ #define _XE_GT_TLB_INVAL_TYPES_H_ +#include #include struct xe_gt; +/** struct xe_tlb_inval - TLB invalidation client */ +struct xe_tlb_inval { + /** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */ +#define TLB_INVALIDATION_SEQNO_MAX 0x100000 + int seqno; + /** + * @tlb_inval.seqno_recv: last received TLB invalidation seqno, + * protected by CT lock + */ + int seqno_recv; + /** + * @tlb_inval.pending_fences: list of pending fences waiting TLB + * invaliations, protected by CT lock + */ + struct list_head pending_fences; + /** + * @tlb_inval.pending_lock: protects @tlb_inval.pending_fences + * and updating @tlb_inval.seqno_recv. + */ + spinlock_t pending_lock; + /** + * @tlb_inval.fence_tdr: schedules a delayed call to + * xe_gt_tlb_fence_timeout after the timeut interval is over. + */ + struct delayed_work fence_tdr; + /** @wtlb_invalidation.wq: schedules GT TLB invalidation jobs */ + struct workqueue_struct *job_wq; + /** @tlb_inval.lock: protects TLB invalidation fences */ + spinlock_t lock; +}; + /** * struct xe_gt_tlb_inval_fence - XE GT TLB invalidation fence * diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h index 38cdca4107c8..ed21bd63b001 100644 --- a/drivers/gpu/drm/xe/xe_gt_types.h +++ b/drivers/gpu/drm/xe/xe_gt_types.h @@ -12,6 +12,7 @@ #include "xe_gt_sriov_pf_types.h" #include "xe_gt_sriov_vf_types.h" #include "xe_gt_stats_types.h" +#include "xe_gt_tlb_inval_types.h" #include "xe_hw_engine_types.h" #include "xe_hw_fence_types.h" #include "xe_oa_types.h" @@ -186,35 +187,7 @@ struct xe_gt { } reset; /** @tlb_inval: TLB invalidation state */ - struct { - /** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */ -#define TLB_INVALIDATION_SEQNO_MAX 0x100000 - int seqno; - /** - * @tlb_inval.seqno_recv: last received TLB invalidation seqno, - * protected by CT lock - */ - int seqno_recv; - /** - * @tlb_inval.pending_fences: list of pending fences waiting TLB - * invaliations, protected by CT lock - */ - struct list_head pending_fences; - /** - * @tlb_inval.pending_lock: protects @tlb_inval.pending_fences - * and updating @tlb_inval.seqno_recv. - */ - spinlock_t pending_lock; - /** - * @tlb_inval.fence_tdr: schedules a delayed call to - * xe_gt_tlb_fence_timeout after the timeut interval is over. - */ - struct delayed_work fence_tdr; - /** @wtlb_invalidation.wq: schedules GT TLB invalidation jobs */ - struct workqueue_struct *job_wq; - /** @tlb_inval.lock: protects TLB invalidation fences */ - spinlock_t lock; - } tlb_inval; + struct xe_tlb_inval tlb_inval; /** * @ccs_mode: Number of compute engines enabled. -- 2.34.1