From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E2AFC87FDA for ; Thu, 7 Aug 2025 19:36:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D022910E8B3; Thu, 7 Aug 2025 19:36:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="D0/15Q1F"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 75CBC10E48D for ; Thu, 7 Aug 2025 19:36:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754595413; x=1786131413; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=aKZtNLvy0Csr7C/A2y4xmmYDl3arFIvSrDSxNZtya0M=; b=D0/15Q1Fom6Y2l0Gt3aeeuxsyJ1t3zOFHfMxEzt3HqcIkn2u29CDCIpK bXzOYDaQYyKCwsFHB4fA9lgn734jCLW/qpT+ADbHfoO9Lyu6OyWNK57eh hMKdnIkCt4Gp3hcam57VXoWAb/Pn2I83PQW9w7yH5ochWC1pQ+5DuWbR+ z7Vlilu+XeXoem25Kv6cvgeXUzVq4ZaHkOX5AX/MulM+7R6mbleMHlRwl lrPyPLpUgFsCR4ieGFcwDxPZKX6fa/RrwZLKIOBSuCcAPbG3qntb2Yln+ jYxb4QiKJX7WferyIWA2Qn+i79WnCVGKTR6zgw8D1XGYxwBegpWxbmyj0 A==; X-CSE-ConnectionGUID: tFJm2lUiSVeqaawEeu3Dkg== X-CSE-MsgGUID: MB/39IcjToSYnUAcSYWNag== X-IronPort-AV: E=McAfee;i="6800,10657,11514"; a="56842539" X-IronPort-AV: E=Sophos;i="6.17,274,1747724400"; d="scan'208";a="56842539" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2025 12:36:52 -0700 X-CSE-ConnectionGUID: bgs6VWqlRjGituv244JpuQ== X-CSE-MsgGUID: Sa8CSu2XQ5OttGIsb79teA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,274,1747724400"; d="scan'208";a="202308326" Received: from dut136arlu.fm.intel.com ([10.105.23.75]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2025 12:36:51 -0700 From: stuartsummers To: Cc: matthew.brost@intel.com, farah.kassabri@intel.com, intel-xe@lists.freedesktop.org, stuartsummers Subject: [PATCH 0/8] Add TLB invalidation abstraction Date: Thu, 7 Aug 2025 19:36:41 +0000 Message-Id: <20250807193649.55399-1-stuart.summers@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" This is a new collection of patches from Matt that has been floating around internally and on the mailing list. The goal here is to abstract the actual mechanism of the invalidation from the higher level invalidation triggers (like page table updates). Most of these were brought in unmodified by Matt, but I've done some minor rebase work here and there and added my signoff where those rebases seemed a little more extensive. Tested on BMG locally. v4: Replace CT lock with seqno_lock v3: Minor spelling fixes and added R-B's per updates on on the mailing list v2: Start the series with a new patch to drop the explicit CT lock (Matt) Pull in the remaining patches from [1] [1] https://patchwork.freedesktop.org/series/151670/#rev1 Matthew Brost (7): drm/xe: s/tlb_invalidation/tlb_inval drm/xe: Add xe_tlb_inval structure drm/xe: Add xe_gt_tlb_invalidation_done_handler drm/xe: Decouple TLB invalidations from GT drm/xe: Prep TLB invalidation fence before sending drm/xe: Add helpers to send TLB invalidations drm/xe: Split TLB invalidation code in frontend and backend stuartsummers (1): drm/xe: Move explicit CT lock in TLB invalidation sequence drivers/gpu/drm/xe/Makefile | 5 +- drivers/gpu/drm/xe/xe_device_types.h | 4 +- drivers/gpu/drm/xe/xe_exec_queue.c | 2 +- drivers/gpu/drm/xe/xe_ggtt.c | 4 +- drivers/gpu/drm/xe/xe_gt.c | 8 +- drivers/gpu/drm/xe/xe_gt_pagefault.c | 1 - drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h | 34 - drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 604 ------------------ drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h | 40 -- .../gpu/drm/xe/xe_gt_tlb_invalidation_types.h | 32 - drivers/gpu/drm/xe/xe_gt_types.h | 33 +- drivers/gpu/drm/xe/xe_guc_ct.c | 8 +- drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 242 +++++++ drivers/gpu/drm/xe/xe_guc_tlb_inval.h | 19 + drivers/gpu/drm/xe/xe_lmtt.c | 12 +- drivers/gpu/drm/xe/xe_migrate.h | 10 +- drivers/gpu/drm/xe/xe_pci.c | 6 +- drivers/gpu/drm/xe/xe_pci_types.h | 2 +- drivers/gpu/drm/xe/xe_pt.c | 63 +- drivers/gpu/drm/xe/xe_svm.c | 3 +- drivers/gpu/drm/xe/xe_tlb_inval.c | 419 ++++++++++++ drivers/gpu/drm/xe/xe_tlb_inval.h | 46 ++ ..._gt_tlb_inval_job.c => xe_tlb_inval_job.c} | 154 +++-- drivers/gpu/drm/xe/xe_tlb_inval_job.h | 33 + drivers/gpu/drm/xe/xe_tlb_inval_types.h | 130 ++++ drivers/gpu/drm/xe/xe_trace.h | 24 +- drivers/gpu/drm/xe/xe_vm.c | 66 +- drivers/gpu/drm/xe/xe_vm.h | 4 +- 28 files changed, 1083 insertions(+), 925 deletions(-) delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h create mode 100644 drivers/gpu/drm/xe/xe_guc_tlb_inval.c create mode 100644 drivers/gpu/drm/xe/xe_guc_tlb_inval.h create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval.c create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval.h rename drivers/gpu/drm/xe/{xe_gt_tlb_inval_job.c => xe_tlb_inval_job.c} (50%) create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval_job.h create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval_types.h -- 2.34.1