From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B529EC87FCB for ; Fri, 8 Aug 2025 07:02:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ukH7h-0006se-Hx; Fri, 08 Aug 2025 03:02:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ukH79-0006AZ-Ql for qemu-arm@nongnu.org; Fri, 08 Aug 2025 03:02:09 -0400 Received: from p-east3-cluster5-host10-snip4-10.eps.apple.com ([57.103.86.231] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ukH77-0005GC-79 for qemu-arm@nongnu.org; Fri, 08 Aug 2025 03:02:07 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-5 (Postfix) with ESMTPS id CFE641800149; Fri, 8 Aug 2025 07:02:01 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=/I/5PhtlXM/BZwPS3Lbq0uAaicCg2NPUGNigbtcBnLU=; h=From:To:Subject:Date:Message-Id:MIME-Version:Content-Type:x-icloud-hme; b=dcBBd/OLFNum4K5D3qwOQpw53GXlVheLWqqhtLOPNU9OJKItSCSC6cxdwxcwGTjmYVa8BrOv3XL615WjPREmdNPPC52LJBGxA9NvHVzvan26mgqtF/y7oY/rf8JdcCUEuMVRGKXP3SCaIxSHD0YrH8GA3oN2TcMxO6CgPLhXUPivrytmajotKgwiJrxzNyqgv54FxHnp1zv2MFzNsIzXQGNiY2oWcqZZYRo86gNIliPhuRsxd5f2IsfWquLPJoElhMXmokFbQly7GCrK68LthMO7yQwrQCNYBCwls260Bbsz1FIY6SXGcr9FUqUGhZn1NZvyfiJ9xPe0r/mdMGK0dw== X-Client-IP: 46.189.47.18 Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-5 (Postfix) with ESMTPSA id 9306E1800121; Fri, 8 Aug 2025 07:01:59 +0000 (UTC) From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Peter Maydell , Shannon Zhao , "Michael S. Tsirkin" , Ani Sinha , qemu-arm@nongnu.org, Paolo Bonzini , Roman Bolshakov , Igor Mammedov , Phil Dennis-Jordan , Alexander Graf , Mads Ynddal , Cameron Esfahani , Mohamed Mediouni , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 11/13] hvf: gate ARM_FEATURE_PMU register emulation behind not being at EL2 Date: Fri, 8 Aug 2025 09:01:35 +0200 Message-Id: <20250808070137.48716-12-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250808070137.48716-1-mohamed@unpredictable.fr> References: <20250808070137.48716-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: -9aeBmNBGmGn1fAl009CZEoxc9_CpGgz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA4MDA1NyBTYWx0ZWRfX7D2C22KmmHda KDqrHcMnWD+yCCrPfhTnE/on5zrHBtwNI7/mps6jEOQFLpOPJgWBmNb4bnNE4FkNYLawDLQmSjy zoaLJiUfRtOZVay7LUint7spmmbUNStT2e6zBiud8YIqfdXaIDp5SV+qLAJ+7VACgew5XcGLcHQ N0JvX2oj+aOoV3UBbpwWWb6t2bKNmlIRT3w/hnezQGuWUiFEvp5+WTGoYyLTK0hkGY7al+gM/xf 1Ti+JR5LcTQH9WB4PDvE1/HUCluTLN7hI8EX4iH1qzjekIgjn/PrErjgcVwFPOFVbcevT1aOw= X-Proofpoint-ORIG-GUID: -9aeBmNBGmGn1fAl009CZEoxc9_CpGgz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_01,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 mlxscore=0 clxscore=1030 malwarescore=0 mlxlogscore=780 suspectscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2508080057 Received-SPF: pass client-ip=57.103.86.231; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org >From Apple documentation: > When EL2 is disabled, PMU register accesses trigger "Trapped MSR, MRS, or > System Instruction" exceptions. When this happens, hv_vcpu_run() returns, and the >  hv_vcpu_exit_t object contains the information about this exception. > When EL2 is enabled, the handling of PMU register accesses is determined by the PMUVer > field of ID_AA64DFR0_EL1 register. > If the PMUVer field value is zero or is invalid, PMU register accesses generate "Undefined" > exceptions, which are sent to the guest. > If the PMUVer field value is non-zero and valid, PMU register accesses are emulated by the framework. > The ID_AA64DFR0_EL1 register can be modified via hv_vcpu_set_sys_reg API. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 41b4321b0b..6da636724b 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1380,7 +1380,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) ARMCPU *arm_cpu = ARM_CPU(cpu); CPUARMState *env = &arm_cpu->env; - if (arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_arm_el2_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCR_EL0: *val = env->cp15.c9_pmcr; @@ -1677,7 +1677,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) SYSREG_OP2(reg), val); - if (arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_arm_el2_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCCNTR_EL0: pmu_op_start(env); -- 2.39.5 (Apple Git-154)