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Tsirkin" , Ani Sinha , qemu-arm@nongnu.org, Paolo Bonzini , Roman Bolshakov , Igor Mammedov , Phil Dennis-Jordan , Alexander Graf , Mads Ynddal , Cameron Esfahani , Mohamed Mediouni , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 02/13] hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU Date: Fri, 8 Aug 2025 09:01:26 +0200 Message-Id: <20250808070137.48716-3-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250808070137.48716-1-mohamed@unpredictable.fr> References: <20250808070137.48716-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: K-SWNKcIemSUvAxHt1g8PMd6u-RxbxsM X-Proofpoint-ORIG-GUID: K-SWNKcIemSUvAxHt1g8PMd6u-RxbxsM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA4MDA1NyBTYWx0ZWRfX8KX2tZnDxpF4 6fTu87Qm+K18fTJuZEvqnNsdin2/KVfrxd6HScurDnBkDAHDntUgvFkrX7nWv4RwuvydJXIkZ1Y sbz3MVYsy56mI+CaasXjQSNMlGSY73nluRqklbsw4tELITXHBifqMFAGKJ4Oll689dA15Vf52M/ K91IngfZHTwO1Pw5UA1rHbJ/wrIZfpQr3SG22owL8IX7HqD6Z5lzVzm6NXEQtPIhLg41XYttaqy Ltm52wWdnAm+7dDuaAWfmMmVPqA8UyAwaBHPvu2xdqH3f2ws/1Go0ibXTmsnUUMOlHALDaKQI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_01,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=0 malwarescore=0 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1030 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2508080057 Received-SPF: pass client-ip=57.103.87.103; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Creating a vCPU locks out APIs such as hv_gic_create(). As a result, switch to using the hv_vcpu_config_get_feature_reg interface. Hardcode MIDR because Apple deliberately doesn't expose a divergent MIDR across systems. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 47b0cd3a35..460782dbc0 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -864,24 +864,24 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { ARMISARegisters host_isar = {}; const struct isar_regs { - int reg; + hv_feature_reg_t reg; uint64_t *val; } regs[] = { - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] }, - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_IDX] }, - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_IDX] }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_IDX] }, /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; - hv_vcpu_t fd; + hv_return_t r = HV_SUCCESS; - hv_vcpu_exit_t *exit; + hv_vcpu_config_t hv_vcpu_config = hv_vcpu_config_create(); int i; ahcf->dtb_compatible = "arm,armv8"; @@ -891,17 +891,11 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) (1ULL << ARM_FEATURE_PMU) | (1ULL << ARM_FEATURE_GENERIC_TIMER); - /* We set up a small vcpu to extract host registers */ - - if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { - return false; - } - for (i = 0; i < ARRAY_SIZE(regs); i++) { - r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); + r |= hv_vcpu_config_get_feature_reg(hv_vcpu_config, regs[i].reg, regs[i].val); } - r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); - r |= hv_vcpu_destroy(fd); + /* post-Armv6, Vendor: Apple (0x61), model and revision not set (all zeroes) */ + ahcf->midr = 0x610f0000; clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); -- 2.39.5 (Apple Git-154)