From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Shannon Zhao" <shannon.zhaosl@gmail.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Ani Sinha" <anisinha@redhat.com>,
qemu-arm@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Roman Bolshakov" <rbolshakov@ddn.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Alexander Graf" <agraf@csgraf.de>,
"Mads Ynddal" <mads@ynddal.dk>,
"Cameron Esfahani" <dirty@apple.com>,
"Mohamed Mediouni" <mohamed@unpredictable.fr>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v6 07/13] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1
Date: Fri, 8 Aug 2025 09:01:31 +0200 [thread overview]
Message-ID: <20250808070137.48716-8-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20250808070137.48716-1-mohamed@unpredictable.fr>
HVF traps accesses to CNTHCTL_EL2. For nested guests, HVF traps accesses to MDCCINT_EL1.
Pass through those accesses to the Hypervisor.framework library.
Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/hvf/hvf.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 3cc6f1e159..788d0d41f4 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -297,6 +297,10 @@ void hvf_arm_init_debug(void)
#define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6)
#define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7)
+/* EL2 registers */
+#define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0)
+#define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0)
+
#define WFX_IS_WFE (1 << 0)
#define TMR_CTL_ENABLE (1 << 0)
@@ -1373,6 +1377,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
case SYSREG_OSDLR_EL1:
/* Dummy register */
return 0;
+ case SYSREG_CNTHCTL_EL2:
+ assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHCTL_EL2, val));
+ return 0;
+ case SYSREG_MDCCINT_EL1:
+ assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCINT_EL1, val));
+ return 0;
case SYSREG_ICC_AP0R0_EL1:
case SYSREG_ICC_AP0R1_EL1:
case SYSREG_ICC_AP0R2_EL1:
@@ -1690,6 +1700,12 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
case SYSREG_OSDLR_EL1:
/* Dummy register */
return 0;
+ case SYSREG_CNTHCTL_EL2:
+ assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHCTL_EL2, val));
+ return 0;
+ case SYSREG_MDCCINT_EL1:
+ assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCINT_EL1, val));
+ return 0;
case SYSREG_LORC_EL1:
/* Dummy register */
return 0;
--
2.39.5 (Apple Git-154)
next prev parent reply other threads:[~2025-08-08 7:03 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-08 7:01 [PATCH v6 00/13] HVF: Add support for platform vGIC and nested virtualisation Mohamed Mediouni
2025-08-08 7:01 ` [PATCH v6 01/13] hw/arm: virt: add GICv2m for the case when ITS is not available Mohamed Mediouni
2025-08-08 7:01 ` [PATCH v6 02/13] hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU Mohamed Mediouni
2025-08-20 12:29 ` Mads Ynddal
2025-08-08 7:01 ` [PATCH v6 03/13] accel, hw/arm, include/system/hvf: infrastructure changes for HVF vGIC Mohamed Mediouni
2025-08-12 13:05 ` Philippe Mathieu-Daudé
2025-08-08 7:01 ` [PATCH v6 04/13] hw/intc: Add hvf vGIC interrupt controller support Mohamed Mediouni
2025-08-12 16:19 ` Philippe Mathieu-Daudé
2025-08-14 12:57 ` Mads Ynddal
2025-08-15 5:55 ` Mohamed Mediouni
2025-08-19 13:21 ` Mads Ynddal
2025-08-08 7:01 ` [PATCH v6 05/13] hw/arm, target/arm: nested virtualisation on HVF Mohamed Mediouni
2025-08-11 12:47 ` Philippe Mathieu-Daudé
2025-08-11 13:35 ` Mohamed Mediouni
2025-08-11 13:40 ` Philippe Mathieu-Daudé
2025-08-11 12:56 ` Philippe Mathieu-Daudé
2025-08-11 13:13 ` Philippe Mathieu-Daudé
2025-08-11 13:35 ` Mohamed Mediouni
2025-08-08 7:01 ` [PATCH v6 06/13] hvf: save/restore Apple GIC state Mohamed Mediouni
2025-08-08 7:01 ` Mohamed Mediouni [this message]
2025-08-08 7:01 ` [PATCH v6 08/13] hw/arm: virt: cleanly fail on attempt to use the platform vGIC together with ITS Mohamed Mediouni
2025-08-08 7:01 ` [PATCH v6 09/13] hvf: only call hvf_sync_vtimer() when running without the platform vGIC Mohamed Mediouni
2025-08-19 12:37 ` Mads Ynddal
2025-08-08 7:01 ` [PATCH v6 10/13] hvf: sync registers used at EL2 Mohamed Mediouni
2025-08-08 7:01 ` [PATCH v6 11/13] hvf: gate ARM_FEATURE_PMU register emulation behind not being " Mohamed Mediouni
2025-08-08 7:01 ` [PATCH v6 12/13] target/arm: hvf: instantiate GIC early Mohamed Mediouni
2025-08-14 13:06 ` Mads Ynddal
2025-08-08 7:01 ` [PATCH v6 13/13] target/arm: hvf: add asserts for code paths not leveraged when using the vGIC Mohamed Mediouni
2025-08-19 12:22 ` Mads Ynddal
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