From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 372A5C87FCF for ; Sat, 9 Aug 2025 13:52:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA4BC10E04A; Sat, 9 Aug 2025 13:52:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OfRV/elH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BA4910E04A; Sat, 9 Aug 2025 13:52:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754747532; x=1786283532; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=q1E+6movKrkbWWn1YIxowCcpYwpJzZ4S/2KgkpxsTZ0=; b=OfRV/elHCs40CDp5OXAQkgQu/eauO+S9jPuoFwYpjOqaUFDn2DIlL1qY RFvQKQxGjKSxkPZWSsdrsVgt/fyNuEJN/Fs5sZOToVup8a/srWC2LSGDq ryR8/wxUWhgvf9s5/xQw3gkFv+hlbKJSTL0GuSP9Oh5Mzwqf3+imPggM1 kg7kRraAGsrO/Ja0kGkM4lLyB9gaV2i9B1TtT9JYlKx+og10ln1YuQ4dV P3fjEZyRamlR8UyWNI+9l5Rj5/Yf+I0w/2mC61d4y4W17Dphhnzl1Mfoj nyFluOSW8MuHRh7xzzX2riVPQEBDrhLbZNUWEY1+MjQycF75haCFkzXC2 g==; X-CSE-ConnectionGUID: kV8TyCLWSHWbt8fftMhkYg== X-CSE-MsgGUID: 8qx3fR6kTeq/J4U/j+CM1w== X-IronPort-AV: E=McAfee;i="6800,10657,11515"; a="68153535" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="68153535" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2025 06:52:11 -0700 X-CSE-ConnectionGUID: 25aNQBvOS2m/jcr0ygh+aQ== X-CSE-MsgGUID: 3sTbtFcQRkOaj6hFjq2FBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="165903733" Received: from smoticic-mobl1.ger.corp.intel.com (HELO fedora) ([10.245.244.28]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2025 06:52:09 -0700 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Matthew Brost , Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , dri-devel@lists.freedesktop.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Christian=20K=C3=B6nig?= Subject: [RFC PATCH 0/6] Multi-pass MMU interval notifiers Date: Sat, 9 Aug 2025 15:51:31 +0200 Message-ID: <20250809135137.259427-1-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.50.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" GPU use-cases for mmu_interval_notifiers with hmm often involve starting a gpu operation and then waiting for it to complete. These operations are typically context preemption or TLB flushing. With single-pass notifiers per GPU this doesn't scale in multi-gpu scenarios. In those scenarios we'd want to first start preemption- or TLB flushing on all GPUs and as a second pass wait for them to complete on all GPUs. One can do this on per-driver basis multiplexing per-driver notifiers but that would mean sharing the notifier "user" lock across all GPUs and that doesn't scale well either, so adding support for multi-pass in the core appears like the right choice. So this series does that, with pach 1 implementing the core support and also describes the choices made. The rest of the patches implements a POC with drm_gpusvm, but this will also come in handy for things like userptr where waiting for bind completion, starting of preemption and waiting for preemption completion can pe pipelined across GPUs. Any feedback or suggestions for alternative approches appreciated. Cc: Matthew Brost Cc: Jason Gunthorpe Cc: Andrew Morton Cc: Simona Vetter Cc: Dave Airlie Cc: Cc: Cc: Matthew Brost (5): drm/gpusvm: Update GPU SVM / Xe to twopass MMU notifier drm/gpusvm: Add drm_gpusvm_in_notifier_* helpers drm/xe: Skip waiting on unarmed fences in xe_gt_tlb_invalidation_fence_wait drm/xe: Add fences argument to xe_vm_range_tilemask_tlb_invalidation drm/xe: Implement two pass MMU notifiers for SVM Thomas Hellström (1): mm/mmu_notifier: Allow multiple struct mmu_interval_notifier passes drivers/gpu/drm/drm_gpusvm.c | 18 +++-- drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h | 3 +- drivers/gpu/drm/xe/xe_svm.c | 84 +++++++++++++++++---- drivers/gpu/drm/xe/xe_vm.c | 26 ++++--- drivers/gpu/drm/xe/xe_vm.h | 6 +- include/drm/drm_gpusvm.h | 33 ++++++-- include/linux/mmu_notifier.h | 30 ++++++++ mm/mmu_notifier.c | 67 +++++++++++++--- 8 files changed, 217 insertions(+), 50 deletions(-) -- 2.50.1